1d3c7f8dc940847c486fa21a53bbbdf049125ce7
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import (TestCase
, ALUHelpers
)
16 from soc
.fu
.trap
.pipeline
import TrapBasePipe
17 from soc
.fu
.trap
.pipe_data
import TrapPipeSpec
21 def get_cu_inputs(dec2
, sim
):
22 """naming (res) must conform to TrapFunctionUnit input regspec
26 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
27 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
28 yield from ALUHelpers
.get_sim_fast_spr1(res
, sim
, dec2
) # SPR1
29 ALUHelpers
.get_sim_cia(res
, sim
, dec2
) # PC
30 ALUHelpers
.get_sim_msr(res
, sim
, dec2
) # MSR
32 print ("alu get_cu_inputs", res
)
38 def set_alu_inputs(alu
, dec2
, sim
):
39 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
40 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
41 # and place it into data_i.b
43 inp
= yield from get_cu_inputs(dec2
, sim
)
44 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
45 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
47 yield from ALUHelpers
.set_cia(alu
, dec2
, inp
)
48 yield from ALUHelpers
.set_msr(alu
, dec2
, inp
)
51 # This test bench is a bit different than is usual. Initially when I
52 # was writing it, I had all of the tests call a function to create a
53 # device under test and simulator, initialize the dut, run the
54 # simulation for ~2 cycles, and assert that the dut output what it
55 # should have. However, this was really slow, since it needed to
56 # create and tear down the dut and simulator for every test case.
58 # Now, instead of doing that, every test case in TrapTestCase puts some
59 # data into the test_data list below, describing the instructions to
60 # be tested and the initial state. Once all the tests have been run,
61 # test_data gets passed to TestRunner which then sets up the DUT and
62 # simulator once, runs all the data through it, and asserts that the
63 # results match the pseudocode sim at every cycle.
65 # By doing this, I've reduced the time it takes to run the test suite
66 # massively. Before, it took around 1 minute on my computer, now it
67 # takes around 3 seconds
70 class TrapTestCase(FHDLTestCase
):
73 def __init__(self
, name
):
74 super().__init
__(name
)
77 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
78 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
)
79 self
.test_data
.append(tc
)
81 def test_1_rfid(self
):
83 initial_regs
= [0] * 32
85 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678}
86 self
.run_tst_program(Program(lst
), initial_regs
, initial_sprs
)
88 def test_0_trap_eq_imm(self
):
91 choice
= random
.choice(insns
)
92 lst
= [f
"{choice} 4, 1, %d" % i
] # TO=4: trap equal
93 initial_regs
= [0] * 32
95 self
.run_tst_program(Program(lst
), initial_regs
)
97 def test_0_trap_eq(self
):
98 insns
= ["twi", "tdi"]
101 lst
= [f
"{choice} 4, 1, 2"] # TO=4: trap equal
102 initial_regs
= [0] * 32
105 self
.run_tst_program(Program(lst
), initial_regs
)
107 def test_ilang(self
):
108 pspec
= TrapPipeSpec(id_wid
=2)
109 alu
= TrapBasePipe(pspec
)
110 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
111 with
open("trap_pipeline.il", "w") as f
:
115 class TestRunner(FHDLTestCase
):
116 def __init__(self
, test_data
):
117 super().__init
__("run_all")
118 self
.test_data
= test_data
123 instruction
= Signal(32)
125 pdecode
= create_pdecode()
127 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
129 pspec
= TrapPipeSpec(id_wid
=2)
130 m
.submodules
.alu
= alu
= TrapBasePipe(pspec
)
132 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
133 comb
+= alu
.p
.valid_i
.eq(1)
134 comb
+= alu
.n
.ready_i
.eq(1)
135 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
140 for test
in self
.test_data
:
142 program
= test
.program
143 self
.subTest(test
.name
)
144 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
146 gen
= program
.generate_instructions()
147 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
149 pc
= sim
.pc
.CIA
.value
151 while index
< len(instructions
):
152 ins
, code
= instructions
[index
]
154 print("pc %08x instr: %08x" % (pc
, ins
& 0xffffffff))
157 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
158 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
159 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
160 print ("before: so/ov/32", so
, ov
, ov32
)
162 # ask the decoder to decode this binary data (endian'd)
163 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
164 yield instruction
.eq(ins
) # raw binary instr.
166 fn_unit
= yield pdecode2
.e
.fn_unit
167 self
.assertEqual(fn_unit
, Function
.TRAP
.value
)
168 yield from set_alu_inputs(alu
, pdecode2
, sim
)
170 opname
= code
.split(' ')[0]
171 yield from sim
.call(opname
)
172 pc
= sim
.pc
.CIA
.value
174 print("pc after %08x" % (pc
))
176 vld
= yield alu
.n
.valid_o
179 vld
= yield alu
.n
.valid_o
182 yield from self
.check_alu_outputs(alu
, pdecode2
, sim
, code
)
184 sim
.add_sync_process(process
)
185 with sim
.write_vcd("alu_simulator.vcd", "simulator.gtkw",
189 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
191 rc
= yield dec2
.e
.rc
.data
192 cridx_ok
= yield dec2
.e
.write_cr
.ok
193 cridx
= yield dec2
.e
.write_cr
.data
195 print ("check extra output", repr(code
), cridx_ok
, cridx
)
197 self
.assertEqual(cridx
, 0, code
)
202 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
203 yield from ALUHelpers
.get_fast_spr1(res
, alu
, dec2
)
204 yield from ALUHelpers
.get_fast_spr2(res
, alu
, dec2
)
205 yield from ALUHelpers
.get_nia(res
, alu
, dec2
)
206 yield from ALUHelpers
.get_msr(res
, alu
, dec2
)
208 print ("output", res
)
210 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
211 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
212 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
213 yield from ALUHelpers
.get_wr_sim_xer_ca(sim_o
, sim
, dec2
)
214 ALUHelpers
.get_sim_cia(sim_o
, sim
, dec2
)
215 ALUHelpers
.get_sim_msr(sim_o
, sim
, dec2
)
217 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
218 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
219 ALUHelpers
.check_xer_ca(self
, res
, sim_o
, code
)
220 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
221 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
224 if __name__
== "__main__":
225 unittest
.main(exit
=False)
226 suite
= unittest
.TestSuite()
227 suite
.addTest(TestRunner(TrapTestCase
.test_data
))
229 runner
= unittest
.TextTestRunner()