4f1af455227285e53ff02f0f2e56a3b0b83cc3c4
[soc.git] / src / soc / fu / trap / test / test_pipe_caller.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil.formaltest import FHDLTestCase
4 from nmigen.cli import rtlil
5 import unittest
6 from soc.decoder.isa.caller import ISACaller, special_sprs
7 from soc.decoder.power_decoder import (create_pdecode)
8 from soc.decoder.power_decoder2 import (PowerDecode2)
9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
10 from soc.decoder.selectable_int import SelectableInt
11 from soc.simulator.program import Program
12 from soc.decoder.isa.all import ISA
13
14
15 from soc.fu.test.common import (TestCase, ALUHelpers)
16 from soc.fu.trap.pipeline import TrapBasePipe
17 from soc.fu.trap.pipe_data import TrapPipeSpec
18 import random
19
20
21 def get_cu_inputs(dec2, sim):
22 """naming (res) must conform to TrapFunctionUnit input regspec
23 """
24 res = {}
25
26 yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
27 yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
28 yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1
29 ALUHelpers.get_sim_cia(res, sim, dec2) # PC
30 ALUHelpers.get_sim_msr(res, sim, dec2) # MSR
31
32 print ("alu get_cu_inputs", res)
33
34 return res
35
36
37
38 def set_alu_inputs(alu, dec2, sim):
39 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
40 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
41 # and place it into data_i.b
42
43 inp = yield from get_cu_inputs(dec2, sim)
44 yield from ALUHelpers.set_int_ra(alu, dec2, inp)
45 yield from ALUHelpers.set_int_rb(alu, dec2, inp)
46
47 yield from ALUHelpers.set_cia(alu, dec2, inp)
48 yield from ALUHelpers.set_msr(alu, dec2, inp)
49
50
51 # This test bench is a bit different than is usual. Initially when I
52 # was writing it, I had all of the tests call a function to create a
53 # device under test and simulator, initialize the dut, run the
54 # simulation for ~2 cycles, and assert that the dut output what it
55 # should have. However, this was really slow, since it needed to
56 # create and tear down the dut and simulator for every test case.
57
58 # Now, instead of doing that, every test case in TrapTestCase puts some
59 # data into the test_data list below, describing the instructions to
60 # be tested and the initial state. Once all the tests have been run,
61 # test_data gets passed to TestRunner which then sets up the DUT and
62 # simulator once, runs all the data through it, and asserts that the
63 # results match the pseudocode sim at every cycle.
64
65 # By doing this, I've reduced the time it takes to run the test suite
66 # massively. Before, it took around 1 minute on my computer, now it
67 # takes around 3 seconds
68
69
70 class TrapTestCase(FHDLTestCase):
71 test_data = []
72
73 def __init__(self, name):
74 super().__init__(name)
75 self.test_name = name
76
77 def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
78 tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
79 self.test_data.append(tc)
80
81 def test_1_rfid(self):
82 lst = ["rfid"]
83 initial_regs = [0] * 32
84 initial_regs[1] = 1
85 self.run_tst_program(Program(lst), initial_regs)
86
87 def test_0_trap_eq_imm(self):
88 insns = ["tw", "td"]
89 for i in range(2):
90 choice = random.choice(insns)
91 lst = [f"{choice} 4, 1, %d" % i] # TO=4: trap equal
92 initial_regs = [0] * 32
93 initial_regs[1] = 1
94 self.run_tst_program(Program(lst), initial_regs)
95
96 def test_0_trap_eq(self):
97 insns = ["twi", "tdi"]
98 for i in range(2):
99 choice = insns[i]
100 lst = [f"{choice} 4, 1, 2"] # TO=4: trap equal
101 initial_regs = [0] * 32
102 initial_regs[1] = 1
103 initial_regs[2] = 1
104 self.run_tst_program(Program(lst), initial_regs)
105
106 def test_ilang(self):
107 pspec = TrapPipeSpec(id_wid=2)
108 alu = TrapBasePipe(pspec)
109 vl = rtlil.convert(alu, ports=alu.ports())
110 with open("trap_pipeline.il", "w") as f:
111 f.write(vl)
112
113
114 class TestRunner(FHDLTestCase):
115 def __init__(self, test_data):
116 super().__init__("run_all")
117 self.test_data = test_data
118
119 def run_all(self):
120 m = Module()
121 comb = m.d.comb
122 instruction = Signal(32)
123
124 pdecode = create_pdecode()
125
126 m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
127
128 pspec = TrapPipeSpec(id_wid=2)
129 m.submodules.alu = alu = TrapBasePipe(pspec)
130
131 comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
132 comb += alu.p.valid_i.eq(1)
133 comb += alu.n.ready_i.eq(1)
134 comb += pdecode2.dec.raw_opcode_in.eq(instruction)
135 sim = Simulator(m)
136
137 sim.add_clock(1e-6)
138 def process():
139 for test in self.test_data:
140 print(test.name)
141 program = test.program
142 self.subTest(test.name)
143 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
144 test.mem, test.msr)
145 gen = program.generate_instructions()
146 instructions = list(zip(gen, program.assembly.splitlines()))
147
148 pc = sim.pc.CIA.value
149 index = pc//4
150 while index < len(instructions):
151 ins, code = instructions[index]
152
153 print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
154 print(code)
155 if 'XER' in sim.spr:
156 so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
157 ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
158 ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
159 print ("before: so/ov/32", so, ov, ov32)
160
161 # ask the decoder to decode this binary data (endian'd)
162 yield pdecode2.dec.bigendian.eq(0) # little / big?
163 yield instruction.eq(ins) # raw binary instr.
164 yield Settle()
165 fn_unit = yield pdecode2.e.fn_unit
166 self.assertEqual(fn_unit, Function.TRAP.value)
167 yield from set_alu_inputs(alu, pdecode2, sim)
168 yield
169 opname = code.split(' ')[0]
170 yield from sim.call(opname)
171 pc = sim.pc.CIA.value
172 index = pc//4
173 print("pc after %08x" % (pc))
174
175 vld = yield alu.n.valid_o
176 while not vld:
177 yield
178 vld = yield alu.n.valid_o
179 yield
180
181 yield from self.check_alu_outputs(alu, pdecode2, sim, code)
182
183 sim.add_sync_process(process)
184 with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
185 traces=[]):
186 sim.run()
187
188 def check_alu_outputs(self, alu, dec2, sim, code):
189
190 rc = yield dec2.e.rc.data
191 cridx_ok = yield dec2.e.write_cr.ok
192 cridx = yield dec2.e.write_cr.data
193
194 print ("check extra output", repr(code), cridx_ok, cridx)
195 if rc:
196 self.assertEqual(cridx, 0, code)
197
198 sim_o = {}
199 res = {}
200
201 yield from ALUHelpers.get_int_o(res, alu, dec2)
202 yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
203 yield from ALUHelpers.get_fast_spr2(res, alu, dec2)
204 yield from ALUHelpers.get_nia(res, alu, dec2)
205 yield from ALUHelpers.get_msr(res, alu, dec2)
206
207 print ("output", res)
208
209 yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
210 yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
211 yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
212 yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
213 ALUHelpers.get_sim_cia(sim_o, sim, dec2)
214 ALUHelpers.get_sim_msr(sim_o, sim, dec2)
215
216 ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
217 ALUHelpers.check_xer_ov(self, res, sim_o, code)
218 ALUHelpers.check_xer_ca(self, res, sim_o, code)
219 ALUHelpers.check_int_o(self, res, sim_o, code)
220 ALUHelpers.check_xer_so(self, res, sim_o, code)
221
222
223 if __name__ == "__main__":
224 unittest.main(exit=False)
225 suite = unittest.TestSuite()
226 suite.addTest(TestRunner(TrapTestCase.test_data))
227
228 runner = unittest.TextTestRunner()
229 runner.run(suite)