6fbf960b109ab91cbb147b2b289a29f7949df583
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import (TestCase
, ALUHelpers
)
16 from soc
.fu
.trap
.pipeline
import TrapBasePipe
17 from soc
.fu
.trap
.pipe_data
import TrapPipeSpec
21 def get_cu_inputs(dec2
, sim
):
22 """naming (res) must conform to TrapFunctionUnit input regspec
26 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
27 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
28 yield from ALUHelpers
.get_sim_fast_spr1(res
, sim
, dec2
) # SPR1
29 yield from ALUHelpers
.get_sim_fast_spr2(res
, sim
, dec2
) # SPR2
30 ALUHelpers
.get_sim_cia(res
, sim
, dec2
) # PC
31 ALUHelpers
.get_sim_msr(res
, sim
, dec2
) # MSR
33 print ("alu get_cu_inputs", res
)
39 def set_alu_inputs(alu
, dec2
, sim
):
40 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
41 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
42 # and place it into data_i.b
44 inp
= yield from get_cu_inputs(dec2
, sim
)
45 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
46 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
47 yield from ALUHelpers
.set_fast_spr1(alu
, dec2
, inp
) # SPR1
48 yield from ALUHelpers
.set_fast_spr2(alu
, dec2
, inp
) # SPR1
50 yield from ALUHelpers
.set_cia(alu
, dec2
, inp
)
51 yield from ALUHelpers
.set_msr(alu
, dec2
, inp
)
54 # This test bench is a bit different than is usual. Initially when I
55 # was writing it, I had all of the tests call a function to create a
56 # device under test and simulator, initialize the dut, run the
57 # simulation for ~2 cycles, and assert that the dut output what it
58 # should have. However, this was really slow, since it needed to
59 # create and tear down the dut and simulator for every test case.
61 # Now, instead of doing that, every test case in TrapTestCase puts some
62 # data into the test_data list below, describing the instructions to
63 # be tested and the initial state. Once all the tests have been run,
64 # test_data gets passed to TestRunner which then sets up the DUT and
65 # simulator once, runs all the data through it, and asserts that the
66 # results match the pseudocode sim at every cycle.
68 # By doing this, I've reduced the time it takes to run the test suite
69 # massively. Before, it took around 1 minute on my computer, now it
70 # takes around 3 seconds
73 class TrapTestCase(FHDLTestCase
):
76 def __init__(self
, name
):
77 super().__init
__(name
)
80 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
81 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
)
82 self
.test_data
.append(tc
)
84 def test_1_rfid(self
):
86 initial_regs
= [0] * 32
88 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678}
89 self
.run_tst_program(Program(lst
), initial_regs
, initial_sprs
)
91 def test_0_trap_eq_imm(self
):
92 insns
= ["twi", "tdi"]
94 choice
= random
.choice(insns
)
95 lst
= [f
"{choice} 4, 1, %d" % i
] # TO=4: trap equal
96 initial_regs
= [0] * 32
98 self
.run_tst_program(Program(lst
), initial_regs
)
100 def test_0_trap_eq(self
):
104 lst
= [f
"{choice} 4, 1, 2"] # TO=4: trap equal
105 initial_regs
= [0] * 32
108 self
.run_tst_program(Program(lst
), initial_regs
)
110 def test_999_illegal(self
):
111 # ok, um this is a bit of a cheat: use an instruction we know
112 # is not implemented by either ISACaller or the core
114 initial_regs
= [0] * 32
115 self
.run_tst_program(Program(lst
), initial_regs
)
117 def test_ilang(self
):
118 pspec
= TrapPipeSpec(id_wid
=2)
119 alu
= TrapBasePipe(pspec
)
120 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
121 with
open("trap_pipeline.il", "w") as f
:
125 class TestRunner(FHDLTestCase
):
126 def __init__(self
, test_data
):
127 super().__init
__("run_all")
128 self
.test_data
= test_data
133 instruction
= Signal(32)
135 pdecode
= create_pdecode()
137 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
139 pspec
= TrapPipeSpec(id_wid
=2)
140 m
.submodules
.alu
= alu
= TrapBasePipe(pspec
)
142 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
143 comb
+= alu
.p
.valid_i
.eq(1)
144 comb
+= alu
.n
.ready_i
.eq(1)
145 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
150 for test
in self
.test_data
:
152 program
= test
.program
153 self
.subTest(test
.name
)
154 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
156 gen
= program
.generate_instructions()
157 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
159 pc
= sim
.pc
.CIA
.value
161 while index
< len(instructions
):
162 ins
, code
= instructions
[index
]
164 print("pc %08x instr: %08x" % (pc
, ins
& 0xffffffff))
167 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
168 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
169 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
170 print ("before: so/ov/32", so
, ov
, ov32
)
172 # ask the decoder to decode this binary data (endian'd)
173 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
174 yield instruction
.eq(ins
) # raw binary instr.
176 fn_unit
= yield pdecode2
.e
.do
.fn_unit
177 self
.assertEqual(fn_unit
, Function
.TRAP
.value
)
178 yield from set_alu_inputs(alu
, pdecode2
, sim
)
180 opname
= code
.split(' ')[0]
181 yield from sim
.call(opname
)
182 pc
= sim
.pc
.CIA
.value
184 print("pc after %08x" % (pc
))
186 vld
= yield alu
.n
.valid_o
189 vld
= yield alu
.n
.valid_o
192 yield from self
.check_alu_outputs(alu
, pdecode2
, sim
, code
)
194 sim
.add_sync_process(process
)
195 with sim
.write_vcd("alu_simulator.vcd", "simulator.gtkw",
199 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
201 rc
= yield dec2
.e
.do
.rc
.data
202 cridx_ok
= yield dec2
.e
.write_cr
.ok
203 cridx
= yield dec2
.e
.write_cr
.data
205 print ("check extra output", repr(code
), cridx_ok
, cridx
)
207 self
.assertEqual(cridx
, 0, code
)
212 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
213 yield from ALUHelpers
.get_fast_spr1(res
, alu
, dec2
)
214 yield from ALUHelpers
.get_fast_spr2(res
, alu
, dec2
)
215 yield from ALUHelpers
.get_nia(res
, alu
, dec2
)
216 yield from ALUHelpers
.get_msr(res
, alu
, dec2
)
218 print ("output", res
)
220 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
221 yield from ALUHelpers
.get_wr_fast_spr1(sim_o
, sim
, dec2
)
222 yield from ALUHelpers
.get_wr_fast_spr2(sim_o
, sim
, dec2
)
223 ALUHelpers
.get_sim_nia(sim_o
, sim
, dec2
)
224 ALUHelpers
.get_sim_msr(sim_o
, sim
, dec2
)
226 print ("sim output", sim_o
)
228 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
229 ALUHelpers
.check_fast_spr1(self
, res
, sim_o
, code
)
230 ALUHelpers
.check_fast_spr2(self
, res
, sim_o
, code
)
231 ALUHelpers
.check_nia(self
, res
, sim_o
, code
)
232 ALUHelpers
.check_msr(self
, res
, sim_o
, code
)
235 if __name__
== "__main__":
236 unittest
.main(exit
=False)
237 suite
= unittest
.TestSuite()
238 suite
.addTest(TestRunner(TrapTestCase
.test_data
))
240 runner
= unittest
.TextTestRunner()