src/soc/fu/trap/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.trap.pipeline import TrapBasePipe
  17 from soc.fu.trap.pipe_data import TrapPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to TrapFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1
  29     yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) # SPR2
  30     ALUHelpers.get_sim_cia(res, sim, dec2) # PC
  31     ALUHelpers.get_sim_msr(res, sim, dec2) # MSR
  32
  33     print ("alu get_cu_inputs", res)
  34
  35     return res
  36
  37
  38
  39 def set_alu_inputs(alu, dec2, sim):
  40     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  41     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  42     # and place it into data_i.b
  43
  44     inp = yield from get_cu_inputs(dec2, sim)
  45     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  46     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  47     yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR1
  48     yield from ALUHelpers.set_fast_spr2(alu, dec2, inp) # SPR1
  49
  50     yield from ALUHelpers.set_cia(alu, dec2, inp)
  51     yield from ALUHelpers.set_msr(alu, dec2, inp)
  52
  53
  54 # This test bench is a bit different than is usual. Initially when I
  55 # was writing it, I had all of the tests call a function to create a
  56 # device under test and simulator, initialize the dut, run the
  57 # simulation for ~2 cycles, and assert that the dut output what it
  58 # should have. However, this was really slow, since it needed to
  59 # create and tear down the dut and simulator for every test case.
  60
  61 # Now, instead of doing that, every test case in TrapTestCase puts some
  62 # data into the test_data list below, describing the instructions to
  63 # be tested and the initial state. Once all the tests have been run,
  64 # test_data gets passed to TestRunner which then sets up the DUT and
  65 # simulator once, runs all the data through it, and asserts that the
  66 # results match the pseudocode sim at every cycle.
  67
  68 # By doing this, I've reduced the time it takes to run the test suite
  69 # massively. Before, it took around 1 minute on my computer, now it
  70 # takes around 3 seconds
  71
  72
  73 class TrapTestCase(FHDLTestCase):
  74     test_data = []
  75
  76     def __init__(self, name):
  77         super().__init__(name)
  78         self.test_name = name
  79
  80     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  81         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  82         self.test_data.append(tc)
  83
  84     def test_1_rfid(self):
  85         lst = ["rfid"]
  86         initial_regs = [0] * 32
  87         initial_regs[1] = 1
  88         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
  89         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
  90
  91     def test_0_trap_eq_imm(self):
  92         insns = ["twi", "tdi"]
  93         for i in range(2):
  94             choice = random.choice(insns)
  95             lst = [f"{choice} 4, 1, %d" % i] # TO=4: trap equal
  96             initial_regs = [0] * 32
  97             initial_regs[1] = 1
  98             self.run_tst_program(Program(lst), initial_regs)
  99
 100     def test_0_trap_eq(self):
 101         insns = ["tw", "td"]
 102         for i in range(2):
 103             choice = insns[i]
 104             lst = [f"{choice} 4, 1, 2"] # TO=4: trap equal
 105             initial_regs = [0] * 32
 106             initial_regs[1] = 1
 107             initial_regs[2] = 1
 108             self.run_tst_program(Program(lst), initial_regs)
 109
 110     def test_ilang(self):
 111         pspec = TrapPipeSpec(id_wid=2)
 112         alu = TrapBasePipe(pspec)
 113         vl = rtlil.convert(alu, ports=alu.ports())
 114         with open("trap_pipeline.il", "w") as f:
 115             f.write(vl)
 116
 117
 118 class TestRunner(FHDLTestCase):
 119     def __init__(self, test_data):
 120         super().__init__("run_all")
 121         self.test_data = test_data
 122
 123     def run_all(self):
 124         m = Module()
 125         comb = m.d.comb
 126         instruction = Signal(32)
 127
 128         pdecode = create_pdecode()
 129
 130         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 131
 132         pspec = TrapPipeSpec(id_wid=2)
 133         m.submodules.alu = alu = TrapBasePipe(pspec)
 134
 135         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 136         comb += alu.p.valid_i.eq(1)
 137         comb += alu.n.ready_i.eq(1)
 138         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 139         sim = Simulator(m)
 140
 141         sim.add_clock(1e-6)
 142         def process():
 143             for test in self.test_data:
 144                 print(test.name)
 145                 program = test.program
 146                 self.subTest(test.name)
 147                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 148                                 test.mem, test.msr)
 149                 gen = program.generate_instructions()
 150                 instructions = list(zip(gen, program.assembly.splitlines()))
 151
 152                 pc = sim.pc.CIA.value
 153                 index = pc//4
 154                 while index < len(instructions):
 155                     ins, code = instructions[index]
 156
 157                     print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
 158                     print(code)
 159                     if 'XER' in sim.spr:
 160                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 161                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 162                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 163                         print ("before: so/ov/32", so, ov, ov32)
 164
 165                     # ask the decoder to decode this binary data (endian'd)
 166                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 167                     yield instruction.eq(ins)          # raw binary instr.
 168                     yield Settle()
 169                     fn_unit = yield pdecode2.e.fn_unit
 170                     self.assertEqual(fn_unit, Function.TRAP.value)
 171                     yield from set_alu_inputs(alu, pdecode2, sim)
 172                     yield
 173                     opname = code.split(' ')[0]
 174                     yield from sim.call(opname)
 175                     pc = sim.pc.CIA.value
 176                     index = pc//4
 177                     print("pc after %08x" % (pc))
 178
 179                     vld = yield alu.n.valid_o
 180                     while not vld:
 181                         yield
 182                         vld = yield alu.n.valid_o
 183                     yield
 184
 185                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 186
 187         sim.add_sync_process(process)
 188         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
 189                             traces=[]):
 190             sim.run()
 191
 192     def check_alu_outputs(self, alu, dec2, sim, code):
 193
 194         rc = yield dec2.e.rc.data
 195         cridx_ok = yield dec2.e.write_cr.ok
 196         cridx = yield dec2.e.write_cr.data
 197
 198         print ("check extra output", repr(code), cridx_ok, cridx)
 199         if rc:
 200             self.assertEqual(cridx, 0, code)
 201
 202         sim_o = {}
 203         res = {}
 204
 205         yield from ALUHelpers.get_int_o(res, alu, dec2)
 206         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
 207         yield from ALUHelpers.get_fast_spr2(res, alu, dec2)
 208         yield from ALUHelpers.get_nia(res, alu, dec2)
 209         yield from ALUHelpers.get_msr(res, alu, dec2)
 210
 211         print ("output", res)
 212
 213         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 214         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
 215         yield from ALUHelpers.get_wr_fast_spr2(sim_o, sim, dec2)
 216         ALUHelpers.get_sim_nia(sim_o, sim, dec2)
 217         ALUHelpers.get_sim_msr(sim_o, sim, dec2)
 218
 219         print ("sim output", sim_o)
 220
 221         ALUHelpers.check_int_o(self, res, sim_o, code)
 222         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
 223         ALUHelpers.check_fast_spr2(self, res, sim_o, code)
 224         ALUHelpers.check_nia(self, res, sim_o, code)
 225
 226
 227 if __name__ == "__main__":
 228     unittest.main(exit=False)
 229     suite = unittest.TestSuite()
 230     suite.addTest(TestRunner(TrapTestCase.test_data))
 231
 232     runner = unittest.TextTestRunner()
 233     runner.run(suite)