src/soc/litex/florent/Makefile

   1 ls180:
   2         ./ls180soc.py --build --platform=ls180
   3         cp build/ls180/gateware/ls180.v .
   4         cp build/ls180/gateware/mem.init .
   5         cp libresoc/libresoc.v .
   6         yosys -p 'read_verilog libresoc.v' \
   7           -p 'write_ilang libresoc_cvt.il'
   8         yosys -p 'read_verilog ls180.v' \
   9           -p 'write_ilang ls180_cvt.il'
  10         yosys -p 'read_ilang ls180_cvt.il' \
  11           -p 'read_ilang libresoc_cvt.il' \
  12           -p 'write_ilang ls180.il'
  13
  14 versaecp5:
  15          ./versa_ecp5.py --sys-clk-freq=55e6 --build
  16
  17 versaecp5load:
  18         ./versa_ecp5.py --sys-clk-freq=55e6 --load