src/soc/litex/florent/Makefile

   1 ls180:
   2         ./ls180soc.py --build --platform=ls180
   3         cp build/ls180/gateware/ls180.v .
   4         cp build/ls180/gateware/mem.init .
   5         cp build/ls180/gateware/mem_1.init .
   6         cp build/ls180/gateware/mem_2.init .
   7         cp build/ls180/gateware/mem_3.init .
   8         cp libresoc/libresoc.v .
   9         yosys -p 'read_verilog libresoc.v' \
  10           -p 'write_ilang libresoc_cvt.il'
  11         yosys -p 'read_verilog ls180.v' \
  12           -p 'write_ilang ls180_cvt.il'
  13         yosys -p 'read_ilang ls180_cvt.il' \
  14           -p 'read_ilang libresoc_cvt.il' \
  15           -p 'write_ilang ls180.il'
  16
  17 versaecp5:
  18          ./versa_ecp5.py --sys-clk-freq=55e6 --build
  19
  20 versaecp5load:
  21         ./versa_ecp5.py --sys-clk-freq=55e6 --load