src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8 from soc.config.pinouts import get_pinspecs
   9 from soc.debug.jtag import Pins
  10 from c4m.nmigen.jtag.tap import IOType
  11
  12 from libresoc.ls180 import io
  13 from litex.build.generic_platform import ConstraintManager
  14
  15
  16 CPU_VARIANTS = ["standard", "standard32", "standardjtag",
  17                 "standardjtagtestgpio", "ls180",
  18                 "standardjtagnoirq"]
  19
  20
  21 def make_wb_bus(prefix, obj, simple=False):
  22     res = {}
  23     outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  24     if not simple:
  25         outpins += ['cti', 'bte']
  26     for o in outpins:
  27         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  28     for i in ['ack', 'err', 'dat_r']:
  29         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  30     return res
  31
  32 def make_wb_slave(prefix, obj):
  33     res = {}
  34     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  35         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  36     for o in ['ack', 'err', 'dat_r']:
  37         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  38     return res
  39
  40 def make_pad(res, dirn, name, suffix, cpup, iop):
  41     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
  42     res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
  43     res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
  44
  45 def get_field(rec, name):
  46     for f in rec.layout:
  47         f = f[0]
  48         if f.endswith(name):
  49             return getattr(rec, f)
  50
  51
  52 def make_jtag_ioconn(res, pin, cpupads, iopads):
  53     (fn, pin, iotype, pin_name, scan_idx) = pin
  54     #serial_tx__core__o, serial_rx__pad__i,
  55     # special-case sdram_clock
  56     if pin == 'clock' and fn == 'sdr':
  57         cpu = cpupads['sdram_clock']
  58         io = iopads['sdram_clock']
  59     else:
  60         cpu = cpupads[fn]
  61         io = iopads[fn]
  62     print ("cpupads", cpupads)
  63     print ("iopads", iopads)
  64     print ("pin", fn, pin, iotype, pin_name)
  65     print ("cpu fn", cpu)
  66     print ("io fn", io)
  67     name = "%s_%s" % (fn, pin)
  68     print ("name", name)
  69     sigs = []
  70
  71     if iotype in (IOType.In, IOType.Out):
  72         ps = pin.split("_")
  73         if pin == 'clock' and fn == 'sdr':
  74             cpup = cpu
  75             iop = io
  76         elif len(ps) == 2 and ps[-1].isdigit():
  77             pin, idx = ps
  78             idx = int(idx)
  79             cpup = getattr(cpu, pin)[idx]
  80             iop = getattr(io, pin)[idx]
  81         elif pin.isdigit():
  82             idx = int(pin)
  83             cpup = cpu[idx]
  84             iop = io[idx]
  85         else:
  86             cpup = getattr(cpu, pin)
  87             iop = getattr(io, pin)
  88
  89     if iotype == IOType.Out:
  90         # output from the pad is routed through C4M JTAG and so
  91         # is an *INPUT* into core.  ls180soc connects this to "real" peripheral
  92         make_pad(res, True, name, "o", cpup, iop)
  93
  94     elif iotype == IOType.In:
  95         # input to the pad is routed through C4M JTAG and so
  96         # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
  97         make_pad(res, False, name, "i", cpup, iop)
  98
  99     elif iotype == IOType.InTriOut:
 100         if fn == 'gpio': # sigh decode GPIO special-case
 101             idx = int(pin[1:])
 102         else:
 103             idx = 0
 104         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
 105         make_pad(res, False, name, "i", cpup, iop)
 106         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
 107         make_pad(res, True, name, "o", cpup, iop)
 108         cpup, iop = get_field(cpu, "oe")[idx], get_field(io, "oe")[idx]
 109         make_pad(res, True, name, "oe", cpup, iop)
 110
 111     if iotype in (IOType.In, IOType.InTriOut):
 112         sigs.append(("i", 1))
 113     if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
 114         sigs.append(("o", 1))
 115     if iotype in (IOType.TriOut, IOType.InTriOut):
 116         sigs.append(("oe", 1))
 117
 118
 119 class LibreSoC(CPU):
 120     name                 = "libre_soc"
 121     human_name           = "Libre-SoC"
 122     variants             = CPU_VARIANTS
 123     endianness           = "little"
 124     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
 125     linker_output_format = "elf64-powerpcle"
 126     nop                  = "nop"
 127     io_regions           = {0xc0000000: 0x10000000} # origin, length
 128
 129     @property
 130     def mem_map(self):
 131         return {"csr": 0xc0000000}
 132
 133     @property
 134     def gcc_flags(self):
 135         flags  = "-m64 "
 136         flags += "-mabi=elfv2 "
 137         flags += "-msoft-float "
 138         flags += "-mno-string "
 139         flags += "-mno-multiple "
 140         flags += "-mno-vsx "
 141         flags += "-mno-altivec "
 142         flags += "-mlittle-endian "
 143         flags += "-mstrict-align "
 144         flags += "-fno-stack-protector "
 145         flags += "-mcmodel=small "
 146         flags += "-D__microwatt__ "
 147         return flags
 148
 149     def __init__(self, platform, variant="standard"):
 150         self.platform     = platform
 151         self.variant      = variant
 152         self.reset        = Signal()
 153         irq_en = "noirq" not in variant
 154
 155         if irq_en:
 156             self.interrupt    = Signal(16)
 157
 158         if variant == "standard32":
 159             self.data_width           = 32
 160             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
 161         else:
 162             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
 163             self.data_width           = 64
 164         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
 165
 166         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
 167         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
 168
 169         jtag_en = ('jtag' in variant) or variant == 'ls180'
 170
 171         if "testgpio" in variant:
 172             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 173         if jtag_en:
 174             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 175
 176         self.periph_buses = [ibus, dbus]
 177         self.memory_buses = []
 178
 179         if jtag_en:
 180             self.periph_buses.append(jtag_wb)
 181             self.jtag_tck = Signal(1)
 182             self.jtag_tms = Signal(1)
 183             self.jtag_tdi = Signal(1)
 184             self.jtag_tdo = Signal(1)
 185         else:
 186             self.dmi_addr = Signal(4)
 187             self.dmi_din = Signal(64)
 188             self.dmi_dout = Signal(64)
 189             self.dmi_wr = Signal(1)
 190             self.dmi_ack = Signal(1)
 191             self.dmi_req = Signal(1)
 192
 193         # # #
 194
 195         self.cpu_params = dict(
 196             # Clock / Reset
 197             i_clk              = ClockSignal(),
 198             i_rst              = ResetSignal() | self.reset,
 199
 200             # Monitoring / Debugging
 201             i_pc_i             = 0,
 202             i_pc_i_ok          = 0,
 203             i_core_bigendian_i = 0, # Signal(),
 204             o_busy_o           = Signal(),   # not connected
 205             o_memerr_o         = Signal(),   # not connected
 206             o_pc_o             = Signal(64), # not connected
 207
 208         )
 209
 210         if irq_en:
 211             # interrupts
 212             self.cpu_params['i_int_level_i'] = self.interrupt
 213
 214         if jtag_en:
 215             self.cpu_params.update(dict(
 216                 # JTAG Debug bus
 217                 o_TAP_bus__tdo = self.jtag_tdo,
 218                 i_TAP_bus__tdi = self.jtag_tdi,
 219                 i_TAP_bus__tms = self.jtag_tms,
 220                 i_TAP_bus__tck = self.jtag_tck,
 221             ))
 222         else:
 223             self.cpu_params.update(dict(
 224                 # DMI Debug bus
 225                 i_dmi_addr_i          = self.dmi_addr,
 226                 i_dmi_din             = self.dmi_din,
 227                 o_dmi_dout            = self.dmi_dout,
 228                 i_dmi_req_i           = self.dmi_req,
 229                 i_dmi_we_i            = self.dmi_wr,
 230                 o_dmi_ack_o           = self.dmi_ack,
 231             ))
 232
 233         # add clock select, pll output
 234         if variant == "ls180":
 235             self.pll_48_o = Signal()
 236             self.clk_sel = Signal(3)
 237             self.cpu_params['i_clk_sel_i'] = self.clk_sel
 238             self.cpu_params['o_pll_48_o'] = self.pll_48_o
 239
 240         # add wishbone buses to cpu params
 241         self.cpu_params.update(make_wb_bus("ibus", ibus))
 242         self.cpu_params.update(make_wb_bus("dbus", dbus))
 243         self.cpu_params.update(make_wb_slave("ics_wb", ics))
 244         self.cpu_params.update(make_wb_slave("icp_wb", icp))
 245         if "testgpio" in variant:
 246             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
 247         if jtag_en:
 248             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 249
 250         if variant == 'ls180':
 251             # urr yuk.  have to expose iopads / pins from core to litex
 252             # then back again.  cut _some_ of that out by connecting
 253             self.padresources = io()
 254             self.pad_cm = ConstraintManager(self.padresources, [])
 255             self.cpupads = {}
 256             iopads = {}
 257             litexmap = {}
 258             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
 259                       'pwm', 'sd0', 'sdr'}
 260             for periph in subset:
 261                 origperiph = periph
 262                 num = None
 263                 if periph[-1].isdigit():
 264                     periph, num = periph[:-1], int(periph[-1])
 265                 print ("periph request", periph, num)
 266                 if periph == 'mspi':
 267                     if num == 0:
 268                         periph, num = 'spimaster', None
 269                     else:
 270                         periph, num = 'spisdcard', None
 271                 elif periph == 'sdr':
 272                     periph = 'sdram'
 273                 elif periph == 'mtwi':
 274                     periph = 'i2c'
 275                 elif periph == 'sd':
 276                     periph, num = 'sdcard', None
 277                 litexmap[origperiph] = (periph, num)
 278                 self.cpupads[origperiph] = platform.request(periph, num)
 279                 iopads[origperiph] = self.pad_cm.request(periph, num)
 280                 if periph == 'sdram':
 281                     # special-case sdram clock
 282                     ck = platform.request("sdram_clock")
 283                     self.cpupads['sdram_clock'] = ck
 284                     ck = self.pad_cm.request("sdram_clock")
 285                     iopads['sdram_clock'] = ck
 286
 287             pinset = get_pinspecs(subset=subset)
 288             p = Pins(pinset)
 289             for pin in list(p):
 290                 make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
 291
 292         # add verilog sources
 293         self.add_sources(platform)
 294
 295     def set_reset_address(self, reset_address):
 296         assert not hasattr(self, "reset_address")
 297         self.reset_address = reset_address
 298         assert reset_address == 0x00000000
 299
 300     @staticmethod
 301     def add_sources(platform):
 302         cdir = os.path.dirname(__file__)
 303         platform.add_source(os.path.join(cdir, "libresoc.v"))
 304
 305     def do_finalize(self):
 306         self.specials += Instance("test_issuer", **self.cpu_params)
 307