src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8 from soc.config.pinouts import get_pinspecs
   9 from soc.debug.jtag import Pins
  10 from c4m.nmigen.jtag.tap import IOType
  11
  12 from libresoc.ls180 import io
  13 from litex.build.generic_platform import ConstraintManager
  14
  15
  16 CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
  17
  18
  19 def make_wb_bus(prefix, obj, simple=False):
  20     res = {}
  21     outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  22     if not simple:
  23         outpins += ['cti', 'bte']
  24     for o in outpins:
  25         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  26     for i in ['ack', 'err', 'dat_r']:
  27         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  28     return res
  29
  30 def make_wb_slave(prefix, obj):
  31     res = {}
  32     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  33         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  34     for o in ['ack', 'err', 'dat_r']:
  35         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  36     return res
  37
  38 def make_pad(res, dirn, name, suffix, cpup, iop):
  39     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
  40     res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
  41     res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
  42
  43 def get_field(rec, name):
  44     for f in rec.layout:
  45         f = f[0]
  46         if f.endswith(name):
  47             return getattr(rec, f)
  48
  49
  50 def make_jtag_ioconn(res, pin, cpupads, iopads):
  51     (fn, pin, iotype, pin_name, scan_idx) = pin
  52     #serial_tx__core__o, serial_rx__pad__i,
  53     # special-case sdram_clock
  54     if pin == 'clock' and fn == 'sdr':
  55         cpu = cpupads['sdram_clock']
  56         io = iopads['sdram_clock']
  57     else:
  58         cpu = cpupads[fn]
  59         io = iopads[fn]
  60     print ("cpupads", cpupads)
  61     print ("iopads", iopads)
  62     print ("pin", fn, pin, iotype, pin_name)
  63     print ("cpu fn", cpu)
  64     print ("io fn", io)
  65     name = "%s_%s" % (fn, pin)
  66     print ("name", name)
  67     sigs = []
  68
  69     if iotype in (IOType.In, IOType.Out):
  70         ps = pin.split("_")
  71         if pin == 'clock' and fn == 'sdr':
  72             cpup = cpu
  73             iop = io
  74         elif len(ps) == 2 and ps[-1].isdigit():
  75             pin, idx = ps
  76             idx = int(idx)
  77             cpup = getattr(cpu, pin)[idx]
  78             iop = getattr(io, pin)[idx]
  79         elif pin.isdigit():
  80             idx = int(pin)
  81             cpup = cpu[idx]
  82             iop = io[idx]
  83         else:
  84             cpup = getattr(cpu, pin)
  85             iop = getattr(io, pin)
  86
  87     if iotype == IOType.Out:
  88         # output from the pad is routed through C4M JTAG and so
  89         # is an *INPUT* into core.  ls180soc connects this to "real" peripheral
  90         make_pad(res, True, name, "o", cpup, iop)
  91
  92     elif iotype == IOType.In:
  93         # input to the pad is routed through C4M JTAG and so
  94         # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
  95         make_pad(res, False, name, "i", cpup, iop)
  96
  97     elif iotype == IOType.InTriOut:
  98         if fn == 'gpio': # sigh decode GPIO special-case
  99             idx = int(pin[1:])
 100         else:
 101             idx = 0
 102         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
 103         make_pad(res, False, name, "i", cpup, iop)
 104         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
 105         make_pad(res, True, name, "o", cpup, iop)
 106         cpup, iop = get_field(cpu, "oe")[idx], get_field(io, "oe")[idx]
 107         make_pad(res, True, name, "oe", cpup, iop)
 108
 109     if iotype in (IOType.In, IOType.InTriOut):
 110         sigs.append(("i", 1))
 111     if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
 112         sigs.append(("o", 1))
 113     if iotype in (IOType.TriOut, IOType.InTriOut):
 114         sigs.append(("oe", 1))
 115
 116
 117 class LibreSoC(CPU):
 118     name                 = "libre_soc"
 119     human_name           = "Libre-SoC"
 120     variants             = CPU_VARIANTS
 121     endianness           = "little"
 122     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
 123     linker_output_format = "elf64-powerpcle"
 124     nop                  = "nop"
 125     io_regions           = {0xc0000000: 0x10000000} # origin, length
 126
 127     @property
 128     def mem_map(self):
 129         return {"csr": 0xc0000000}
 130
 131     @property
 132     def gcc_flags(self):
 133         flags  = "-m64 "
 134         flags += "-mabi=elfv2 "
 135         flags += "-msoft-float "
 136         flags += "-mno-string "
 137         flags += "-mno-multiple "
 138         flags += "-mno-vsx "
 139         flags += "-mno-altivec "
 140         flags += "-mlittle-endian "
 141         flags += "-mstrict-align "
 142         flags += "-fno-stack-protector "
 143         flags += "-mcmodel=small "
 144         flags += "-D__microwatt__ "
 145         return flags
 146
 147     def __init__(self, platform, variant="standard"):
 148         self.platform     = platform
 149         self.variant      = variant
 150         self.reset        = Signal()
 151         irq_en = "noirq" not in variant
 152
 153         if irq_en:
 154             self.interrupt    = Signal(16)
 155
 156         if variant == "standard32":
 157             self.data_width           = 32
 158             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
 159         else:
 160             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
 161             self.data_width           = 64
 162         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
 163
 164         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
 165         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
 166
 167         jtag_en = ('jtag' in variant) or variant == 'ls180'
 168
 169         if "gpiotest" in variant:
 170             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 171         if jtag_en:
 172             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 173
 174         self.periph_buses = [ibus, dbus]
 175         self.memory_buses = []
 176
 177         if jtag_en:
 178             self.periph_buses.append(jtag_wb)
 179             self.jtag_tck = Signal(1)
 180             self.jtag_tms = Signal(1)
 181             self.jtag_tdi = Signal(1)
 182             self.jtag_tdo = Signal(1)
 183         else:
 184             self.dmi_addr = Signal(4)
 185             self.dmi_din = Signal(64)
 186             self.dmi_dout = Signal(64)
 187             self.dmi_wr = Signal(1)
 188             self.dmi_ack = Signal(1)
 189             self.dmi_req = Signal(1)
 190
 191         # # #
 192
 193         self.cpu_params = dict(
 194             # Clock / Reset
 195             i_clk              = ClockSignal(),
 196             i_rst              = ResetSignal() | self.reset,
 197
 198             # Monitoring / Debugging
 199             i_pc_i             = 0,
 200             i_pc_i_ok          = 0,
 201             i_core_bigendian_i = 0, # Signal(),
 202             o_busy_o           = Signal(),   # not connected
 203             o_memerr_o         = Signal(),   # not connected
 204             o_pc_o             = Signal(64), # not connected
 205
 206         )
 207
 208         if irq_en:
 209             # interrupts
 210             self.cpu_params['i_int_level_i'] = self.interrupt
 211
 212         if jtag_en:
 213             self.cpu_params.update(dict(
 214                 # JTAG Debug bus
 215                 o_TAP_bus__tdo = self.jtag_tdo,
 216                 i_TAP_bus__tdi = self.jtag_tdi,
 217                 i_TAP_bus__tms = self.jtag_tms,
 218                 i_TAP_bus__tck = self.jtag_tck,
 219             ))
 220         else:
 221             self.cpu_params.update(dict(
 222                 # DMI Debug bus
 223                 i_dmi_addr_i          = self.dmi_addr,
 224                 i_dmi_din             = self.dmi_din,
 225                 o_dmi_dout            = self.dmi_dout,
 226                 i_dmi_req_i           = self.dmi_req,
 227                 i_dmi_we_i            = self.dmi_wr,
 228                 o_dmi_ack_o           = self.dmi_ack,
 229             ))
 230
 231         # add clock select, pll output
 232         if variant == "ls180":
 233             self.pll_48_o = Signal()
 234             self.clk_sel = Signal(3)
 235             self.cpu_params['i_clk_sel_i'] = self.clk_sel
 236             self.cpu_params['o_pll_48_o'] = self.pll_48_o
 237
 238         # add wishbone buses to cpu params
 239         self.cpu_params.update(make_wb_bus("ibus", ibus))
 240         self.cpu_params.update(make_wb_bus("dbus", dbus))
 241         self.cpu_params.update(make_wb_slave("ics_wb", ics))
 242         self.cpu_params.update(make_wb_slave("icp_wb", icp))
 243         if "gpiotest" in variant:
 244             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
 245         if jtag_en:
 246             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 247
 248         if variant == 'ls180':
 249             # urr yuk.  have to expose iopads / pins from core to litex
 250             # then back again.  cut _some_ of that out by connecting
 251             self.padresources = io()
 252             self.pad_cm = ConstraintManager(self.padresources, [])
 253             self.cpupads = {}
 254             iopads = {}
 255             litexmap = {}
 256             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
 257                       'pwm', 'sd0', 'sdr'}
 258             for periph in subset:
 259                 origperiph = periph
 260                 num = None
 261                 if periph[-1].isdigit():
 262                     periph, num = periph[:-1], int(periph[-1])
 263                 print ("periph request", periph, num)
 264                 if periph == 'mspi':
 265                     if num == 0:
 266                         periph, num = 'spimaster', None
 267                     else:
 268                         periph, num = 'spisdcard', None
 269                 elif periph == 'sdr':
 270                     periph = 'sdram'
 271                 elif periph == 'mtwi':
 272                     periph = 'i2c'
 273                 elif periph == 'sd':
 274                     periph, num = 'sdcard', None
 275                 litexmap[origperiph] = (periph, num)
 276                 self.cpupads[origperiph] = platform.request(periph, num)
 277                 iopads[origperiph] = self.pad_cm.request(periph, num)
 278                 if periph == 'sdram':
 279                     # special-case sdram clock
 280                     ck = platform.request("sdram_clock")
 281                     self.cpupads['sdram_clock'] = ck
 282                     ck = self.pad_cm.request("sdram_clock")
 283                     iopads['sdram_clock'] = ck
 284
 285             pinset = get_pinspecs(subset=subset)
 286             p = Pins(pinset)
 287             for pin in list(p):
 288                 make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
 289
 290         # add verilog sources
 291         self.add_sources(platform)
 292
 293     def set_reset_address(self, reset_address):
 294         assert not hasattr(self, "reset_address")
 295         self.reset_address = reset_address
 296         assert reset_address == 0x00000000
 297
 298     @staticmethod
 299     def add_sources(platform):
 300         cdir = os.path.dirname(__file__)
 301         platform.add_source(os.path.join(cdir, "libresoc.v"))
 302
 303     def do_finalize(self):
 304         self.specials += Instance("test_issuer", **self.cpu_params)
 305