3 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
5 from litex
.soc
.interconnect
import wishbone
as wb
6 from litex
.soc
.cores
.cpu
import CPU
8 from soc
.config
.pinouts
import get_pinspecs
9 from soc
.debug
.jtag
import Pins
10 from c4m
.nmigen
.jtag
.tap
import IOType
12 from libresoc
.ls180
import io
13 from litex
.build
.generic_platform
import ConstraintManager
16 CPU_VARIANTS
= ["standard", "standard32", "standardjtag", "ls180"]
19 def make_wb_bus(prefix
, obj
, simple
=False):
21 outpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
23 outpins
+= ['cti', 'bte']
25 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
26 for i
in ['ack', 'err', 'dat_r']:
27 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
30 def make_wb_slave(prefix
, obj
):
32 for i
in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
33 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
34 for o
in ['ack', 'err', 'dat_r']:
35 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
38 def make_pad(res
, dirn
, name
, suffix
, cpup
, iop
):
39 cpud
, iod
= ('i', 'o') if dirn
else ('o', 'i')
40 res
['%s_%s__core__%s' % (cpud
, name
, suffix
)] = cpup
41 res
['%s_%s__pad__%s' % (iod
, name
, suffix
)] = iop
43 def get_field(rec
, name
):
47 return getattr(rec
, f
)
50 def make_jtag_ioconn(res
, pin
, cpupads
, iopads
):
51 (fn
, pin
, iotype
, pin_name
, scan_idx
) = pin
52 #serial_tx__core__o, serial_rx__pad__i,
53 print ("cpupads", cpupads
)
54 print ("iopads", iopads
)
55 print ("pin", fn
, pin
, iotype
, pin_name
)
62 name
= "%s_%s" % (fn
, pin
)
64 if iotype
in (IOType
.In
, IOType
.Out
):
70 cpup
= getattr(cpu
, pin
)
71 iop
= getattr(io
, pin
)
73 if iotype
== IOType
.Out
:
74 # output from the pad is routed through C4M JTAG and so
75 # is an *INPUT* into core. ls180soc connects this to "real" peripheral
76 make_pad(res
, True, name
, "o", cpup
, iop
)
78 elif iotype
== IOType
.In
:
79 # input to the pad is routed through C4M JTAG and so
80 # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
81 make_pad(res
, False, name
, "i", cpup
, iop
)
83 elif iotype
== IOType
.InTriOut
:
84 if fn
== 'gpio': # sigh decode GPIO special-case
88 cpup
, iop
= get_field(cpu
, "i")[idx
], get_field(io
, "i")[idx
]
89 make_pad(res
, False, name
, "i", cpup
, iop
)
90 cpup
, iop
= get_field(cpu
, "o")[idx
], get_field(io
, "o")[idx
]
91 make_pad(res
, True, name
, "o", cpup
, iop
)
92 cpup
, iop
= get_field(cpu
, "oe")[idx
], get_field(io
, "oe")[idx
]
93 make_pad(res
, True, name
, "oe", cpup
, iop
)
95 if iotype
in (IOType
.In
, IOType
.InTriOut
):
97 if iotype
in (IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
):
99 if iotype
in (IOType
.TriOut
, IOType
.InTriOut
):
100 sigs
.append(("oe", 1))
105 human_name
= "Libre-SoC"
106 variants
= CPU_VARIANTS
107 endianness
= "little"
108 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu")
109 linker_output_format
= "elf64-powerpcle"
111 io_regions
= {0xc0000000: 0x10000000} # origin, length
115 return {"csr": 0xc0000000}
120 flags
+= "-mabi=elfv2 "
121 flags
+= "-msoft-float "
122 flags
+= "-mno-string "
123 flags
+= "-mno-multiple "
125 flags
+= "-mno-altivec "
126 flags
+= "-mlittle-endian "
127 flags
+= "-mstrict-align "
128 flags
+= "-fno-stack-protector "
129 flags
+= "-mcmodel=small "
130 flags
+= "-D__microwatt__ "
133 def __init__(self
, platform
, variant
="standard"):
134 self
.platform
= platform
135 self
.variant
= variant
136 self
.reset
= Signal()
137 self
.interrupt
= Signal(16)
139 if variant
== "standard32":
141 self
.dbus
= dbus
= wb
.Interface(data_width
=32, adr_width
=30)
143 self
.dbus
= dbus
= wb
.Interface(data_width
=64, adr_width
=29)
145 self
.ibus
= ibus
= wb
.Interface(data_width
=64, adr_width
=29)
147 self
.xics_icp
= icp
= wb
.Interface(data_width
=32, adr_width
=30)
148 self
.xics_ics
= ics
= wb
.Interface(data_width
=32, adr_width
=30)
150 jtag_en
= ('jtag' in variant
) or variant
== 'ls180'
152 if variant
!= "ls180":
153 self
.simple_gpio
= gpio
= wb
.Interface(data_width
=32, adr_width
=30)
155 self
.jtag_wb
= jtag_wb
= wb
.Interface(data_width
=64, adr_width
=29)
157 self
.periph_buses
= [ibus
, dbus
]
158 self
.memory_buses
= []
161 self
.periph_buses
.append(jtag_wb
)
162 self
.jtag_tck
= Signal(1)
163 self
.jtag_tms
= Signal(1)
164 self
.jtag_tdi
= Signal(1)
165 self
.jtag_tdo
= Signal(1)
167 self
.dmi_addr
= Signal(4)
168 self
.dmi_din
= Signal(64)
169 self
.dmi_dout
= Signal(64)
170 self
.dmi_wr
= Signal(1)
171 self
.dmi_ack
= Signal(1)
172 self
.dmi_req
= Signal(1)
176 self
.cpu_params
= dict(
178 i_clk
= ClockSignal(),
179 i_rst
= ResetSignal() | self
.reset
,
181 # Monitoring / Debugging
184 i_core_bigendian_i
= 0, # Signal(),
185 o_busy_o
= Signal(), # not connected
186 o_memerr_o
= Signal(), # not connected
187 o_pc_o
= Signal(64), # not connected
190 i_int_level_i
= self
.interrupt
,
195 self
.cpu_params
.update(dict(
197 o_TAP_bus__tdo
= self
.jtag_tdo
,
198 i_TAP_bus__tdi
= self
.jtag_tdi
,
199 i_TAP_bus__tms
= self
.jtag_tms
,
200 i_TAP_bus__tck
= self
.jtag_tck
,
203 self
.cpu_params
.update(dict(
205 i_dmi_addr_i
= self
.dmi_addr
,
206 i_dmi_din
= self
.dmi_din
,
207 o_dmi_dout
= self
.dmi_dout
,
208 i_dmi_req_i
= self
.dmi_req
,
209 i_dmi_we_i
= self
.dmi_wr
,
210 o_dmi_ack_o
= self
.dmi_ack
,
213 # add clock select, pll output
214 if variant
== "ls180":
215 self
.pll_48_o
= Signal()
216 self
.clk_sel
= Signal(3)
217 self
.cpu_params
['i_clk_sel_i'] = self
.clk_sel
218 self
.cpu_params
['o_pll_48_o'] = self
.pll_48_o
220 # add wishbone buses to cpu params
221 self
.cpu_params
.update(make_wb_bus("ibus", ibus
))
222 self
.cpu_params
.update(make_wb_bus("dbus", dbus
))
223 self
.cpu_params
.update(make_wb_slave("ics_wb", ics
))
224 self
.cpu_params
.update(make_wb_slave("icp_wb", icp
))
225 if variant
!= "ls180":
226 self
.cpu_params
.update(make_wb_slave("gpio_wb", gpio
))
228 self
.cpu_params
.update(make_wb_bus("jtag_wb", jtag_wb
, simple
=True))
230 if variant
== 'ls180':
231 # urr yuk. have to expose iopads / pins from core to litex
232 # then back again. cut _some_ of that out by connecting
233 self
.padresources
= io()
234 self
.pad_cm
= ConstraintManager(self
.padresources
, [])
238 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
239 'pwm', 'sd0'}#, 'sdr'}
240 for periph
in subset
:
243 if periph
[-1].isdigit():
244 periph
, num
= periph
[:-1], int(periph
[-1])
245 print ("periph request", periph
, num
)
248 periph
, num
= 'spimaster', None
250 periph
, num
= 'spisdcard', None
251 elif periph
== 'mtwi':
254 periph
, num
= 'sdcard', None
255 litexmap
[origperiph
] = (periph
, num
)
256 self
.cpupads
[origperiph
] = platform
.request(periph
, num
)
257 iopads
[origperiph
] = self
.pad_cm
.request(periph
, num
)
259 pinset
= get_pinspecs(subset
=subset
)
262 make_jtag_ioconn(self
.cpu_params
, pin
, self
.cpupads
, iopads
)
264 # add verilog sources
265 self
.add_sources(platform
)
267 def set_reset_address(self
, reset_address
):
268 assert not hasattr(self
, "reset_address")
269 self
.reset_address
= reset_address
270 assert reset_address
== 0x00000000
273 def add_sources(platform
):
274 cdir
= os
.path
.dirname(__file__
)
275 platform
.add_source(os
.path
.join(cdir
, "libresoc.v"))
277 def do_finalize(self
):
278 self
.specials
+= Instance("test_issuer", **self
.cpu_params
)