src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone
   6 from litex.soc.cores.cpu import CPU
   7
   8 CPU_VARIANTS = ["standard"]
   9
  10
  11 class LibreSoC(CPU):
  12     name                 = "libre_soc"
  13     human_name           = "Libre-SoC"
  14     variants             = CPU_VARIANTS
  15     data_width           = 64
  16     endianness           = "little"
  17     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  18     linker_output_format = "elf64-powerpcle"
  19     nop                  = "nop"
  20     io_regions           = {0xc0000000: 0x10000000} # origin, length
  21
  22     @property
  23     def mem_map(self):
  24         return {"csr": 0xc0000000}
  25
  26     @property
  27     def gcc_flags(self):
  28         flags  = "-m64 "
  29         flags += "-mabi=elfv2 "
  30         flags += "-msoft-float "
  31         flags += "-mno-string "
  32         flags += "-mno-multiple "
  33         flags += "-mno-vsx "
  34         flags += "-mno-altivec "
  35         flags += "-mlittle-endian "
  36         flags += "-mstrict-align "
  37         flags += "-fno-stack-protector "
  38         flags += "-mcmodel=small "
  39         flags += "-D__microwatt__ "
  40         return flags
  41
  42     def __init__(self, platform, variant="standard"):
  43         self.platform     = platform
  44         self.variant      = variant
  45         self.reset        = Signal()
  46
  47         self.ibus         = wishbone.Interface(data_width=64, adr_width=29)
  48         self.dbus         = wishbone.Interface(data_width=64, adr_width=29)
  49
  50         self.periph_buses = [self.ibus, self.dbus]
  51         self.memory_buses = []
  52
  53         # # #
  54
  55         self.cpu_params = dict(
  56             # Clock / Reset
  57             i_clk              = ClockSignal(),
  58             i_rst              = ResetSignal() | self.reset,
  59
  60             # IBus
  61             o_ibus__stb        = self.ibus.stb,
  62             o_ibus__cyc        = self.ibus.cyc,
  63             o_ibus__cti        = self.ibus.cti,
  64             o_ibus__bte        = self.ibus.bte,
  65             o_ibus__we         = self.ibus.we,
  66             o_ibus__adr        = Cat(self.ibus.adr), # bytes to words addressing
  67             o_ibus__dat_w      = self.ibus.dat_w,
  68             o_ibus__sel        = self.ibus.sel,
  69             i_ibus__ack        = self.ibus.ack,
  70             i_ibus__err        = self.ibus.err,
  71             i_ibus__dat_r      = self.ibus.dat_r,
  72
  73             # DBus
  74             o_dbus__stb        = self.dbus.stb,
  75             o_dbus__cyc        = self.dbus.cyc,
  76             o_dbus__cti        = self.dbus.cti,
  77             o_dbus__bte        = self.dbus.bte,
  78             o_dbus__we         = self.dbus.we,
  79             o_dbus__adr        = Cat(self.dbus.adr), # bytes to words addressing
  80             o_dbus__dat_w      = self.dbus.dat_w,
  81             o_dbus__sel        = self.dbus.sel,
  82             i_dbus__ack        = self.dbus.ack,
  83             i_dbus__err        = self.dbus.err,
  84             i_dbus__dat_r      = self.dbus.dat_r,
  85
  86             # Monitoring / Debugging
  87             i_go_insn_i        = 1,
  88             i_pc_i             = 0,
  89             i_pc_i_ok          = 0,
  90             i_core_start_i     = Signal(),
  91             i_core_stop_i      = Signal(),
  92             i_core_bigendian_i = 0, # Signal(),
  93             o_halted_o         = Signal(),
  94             o_busy_o           = Signal()
  95         )
  96
  97         # add verilog sources
  98         self.add_sources(platform)
  99
 100     def set_reset_address(self, reset_address):
 101         assert not hasattr(self, "reset_address")
 102         self.reset_address = reset_address
 103         assert reset_address == 0x00000000
 104
 105     @staticmethod
 106     def add_sources(platform):
 107         cdir = os.path.dirname(__file__)
 108         platform.add_source(os.path.join(cdir, "libresoc.v"))
 109
 110     def do_finalize(self):
 111         self.specials += Instance("test_issuer", **self.cpu_params)
 112