src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8 CPU_VARIANTS = ["standard", "standard32", "ls180"]
   9
  10
  11 def make_wb_bus(prefix, obj):
  12     res = {}
  13     for o in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  14         res['o_%s_%s' % (prefix, o)] = getattr(obj, o)
  15     for i in ['ack', 'err', 'dat_r']:
  16         res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
  17     return res
  18
  19 def make_wb_slave(prefix, obj):
  20     res = {}
  21     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  22         res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
  23     for o in ['ack', 'err', 'dat_r']:
  24         res['o_%s_%s' % (prefix, o)] = getattr(obj, o)
  25     return res
  26
  27
  28 class LibreSoC(CPU):
  29     name                 = "libre_soc"
  30     human_name           = "Libre-SoC"
  31     variants             = CPU_VARIANTS
  32     endianness           = "little"
  33     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  34     linker_output_format = "elf64-powerpcle"
  35     nop                  = "nop"
  36     io_regions           = {0xc0000000: 0x10000000} # origin, length
  37
  38     @property
  39     def mem_map(self):
  40         return {"csr": 0xc0000000}
  41
  42     @property
  43     def gcc_flags(self):
  44         flags  = "-m64 "
  45         flags += "-mabi=elfv2 "
  46         flags += "-msoft-float "
  47         flags += "-mno-string "
  48         flags += "-mno-multiple "
  49         flags += "-mno-vsx "
  50         flags += "-mno-altivec "
  51         flags += "-mlittle-endian "
  52         flags += "-mstrict-align "
  53         flags += "-fno-stack-protector "
  54         flags += "-mcmodel=small "
  55         flags += "-D__microwatt__ "
  56         return flags
  57
  58     def __init__(self, platform, variant="standard"):
  59         self.platform     = platform
  60         self.variant      = variant
  61         self.reset        = Signal()
  62         self.interrupt    = Signal(16)
  63
  64         if variant == "standard32":
  65             self.data_width           = 32
  66             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
  67         else:
  68             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
  69             self.data_width           = 64
  70         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
  71
  72         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
  73         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
  74
  75         if variant != "ls180":
  76             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
  77
  78         self.periph_buses = [ibus, dbus]
  79         self.memory_buses = []
  80
  81         self.dmi_addr = Signal(4)
  82         self.dmi_din = Signal(64)
  83         self.dmi_dout = Signal(64)
  84         self.dmi_wr = Signal(1)
  85         self.dmi_ack = Signal(1)
  86         self.dmi_req = Signal(1)
  87
  88         # # #
  89
  90         self.cpu_params = dict(
  91             # Clock / Reset
  92             i_clk              = ClockSignal(),
  93             i_rst              = ResetSignal() | self.reset,
  94
  95             # Monitoring / Debugging
  96             i_pc_i             = 0,
  97             i_pc_i_ok          = 0,
  98             i_core_bigendian_i = 0, # Signal(),
  99             o_busy_o           = Signal(),   # not connected
 100             o_memerr_o         = Signal(),   # not connected
 101             o_pc_o             = Signal(64), # not connected
 102
 103             # interrupts
 104             i_int_level_i      = self.interrupt,
 105
 106             # Debug bus
 107             i_dmi_addr_i          = self.dmi_addr,
 108             i_dmi_din             = self.dmi_din,
 109             o_dmi_dout            = self.dmi_dout,
 110             i_dmi_req_i           = self.dmi_req,
 111             i_dmi_we_i            = self.dmi_wr,
 112             o_dmi_ack_o           = self.dmi_ack,
 113         )
 114
 115         # add wishbone buses to cpu params
 116         self.cpu_params.update(make_wb_bus("ibus_", ibus))
 117         self.cpu_params.update(make_wb_bus("dbus_", dbus))
 118         self.cpu_params.update(make_wb_slave("ics_wb_", ics))
 119         self.cpu_params.update(make_wb_slave("icp_wb_", icp))
 120         if variant != "ls180":
 121             self.cpu_params.update(make_wb_slave("gpio_wb_", gpio))
 122
 123         # add verilog sources
 124         self.add_sources(platform)
 125
 126     def set_reset_address(self, reset_address):
 127         assert not hasattr(self, "reset_address")
 128         self.reset_address = reset_address
 129         assert reset_address == 0x00000000
 130
 131     @staticmethod
 132     def add_sources(platform):
 133         cdir = os.path.dirname(__file__)
 134         platform.add_source(os.path.join(cdir, "libresoc.v"))
 135
 136     def do_finalize(self):
 137         self.specials += Instance("test_issuer", **self.cpu_params)
 138