src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone
   6 from litex.soc.cores.cpu import CPU
   7
   8 CPU_VARIANTS = ["standard", "standard32"]
   9
  10
  11 def make_wb_bus(prefix, obj):
  12     res = {}
  13     for o in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  14         res['o_%s_%s' % (prefix, o)] = getattr(obj, o)
  15     for i in ['ack', 'err', 'dat_r']:
  16         res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
  17     return res
  18
  19
  20 class LibreSoC(CPU):
  21     name                 = "libre_soc"
  22     human_name           = "Libre-SoC"
  23     variants             = CPU_VARIANTS
  24     endianness           = "little"
  25     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  26     linker_output_format = "elf64-powerpcle"
  27     nop                  = "nop"
  28     io_regions           = {0xc0000000: 0x10000000} # origin, length
  29
  30     @property
  31     def mem_map(self):
  32         return {"csr": 0xc0000000}
  33
  34     @property
  35     def gcc_flags(self):
  36         flags  = "-m64 "
  37         flags += "-mabi=elfv2 "
  38         flags += "-msoft-float "
  39         flags += "-mno-string "
  40         flags += "-mno-multiple "
  41         flags += "-mno-vsx "
  42         flags += "-mno-altivec "
  43         flags += "-mlittle-endian "
  44         flags += "-mstrict-align "
  45         flags += "-fno-stack-protector "
  46         flags += "-mcmodel=small "
  47         flags += "-D__microwatt__ "
  48         return flags
  49
  50     def __init__(self, platform, variant="standard"):
  51         self.platform     = platform
  52         self.variant      = variant
  53         self.reset        = Signal()
  54         self.interrupt    = Signal(16)
  55
  56         if variant == "standard32":
  57             self.data_width           = 32
  58             self.dbus = dbus = wishbone.Interface(data_width=32, adr_width=30)
  59         else:
  60             self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
  61             self.data_width           = 64
  62         self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
  63
  64         self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=5)
  65         self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=14)
  66
  67         self.ics_buses = [icp, ics]
  68         self.periph_buses = [ibus, dbus]
  69         self.memory_buses = []
  70
  71         self.dmi_addr = Signal(4)
  72         self.dmi_din = Signal(64)
  73         self.dmi_dout = Signal(64)
  74         self.dmi_wr = Signal(1)
  75         self.dmi_ack = Signal(1)
  76         self.dmi_req = Signal(1)
  77
  78         # # #
  79
  80         self.cpu_params = dict(
  81             # Clock / Reset
  82             i_clk              = ClockSignal(),
  83             i_rst              = ResetSignal() | self.reset,
  84
  85             # Monitoring / Debugging
  86             i_pc_i             = 0,
  87             i_pc_i_ok          = 0,
  88             i_core_bigendian_i = 0, # Signal(),
  89             o_busy_o           = Signal(),
  90             o_memerr_o         = Signal(),
  91
  92             # interrupts
  93             i_int_level_i      = self.interrupt,
  94
  95             # Debug bus
  96             i_dmi_addr_i          = self.dmi_addr,
  97             i_dmi_din             = self.dmi_din,
  98             o_dmi_dout            = self.dmi_dout,
  99             i_dmi_req_i           = self.dmi_req,
 100             i_dmi_we_i            = self.dmi_wr,
 101             o_dmi_ack_o           = self.dmi_ack,
 102         )
 103
 104         # add wishbone buses to cpu params
 105         self.cpu_params.update(make_wb_bus("ibus_", ibus))
 106         self.cpu_params.update(make_wb_bus("dbus_", dbus))
 107         self.cpu_params.update(make_wb_bus("ics_wb_", ics))
 108         self.cpu_params.update(make_wb_bus("icp_wb_", icp))
 109
 110         # add verilog sources
 111         self.add_sources(platform)
 112
 113     def set_reset_address(self, reset_address):
 114         assert not hasattr(self, "reset_address")
 115         self.reset_address = reset_address
 116         assert reset_address == 0x00000000
 117
 118     @staticmethod
 119     def add_sources(platform):
 120         cdir = os.path.dirname(__file__)
 121         platform.add_source(os.path.join(cdir, "libresoc.v"))
 122
 123     def do_finalize(self):
 124         self.specials += Instance("test_issuer", **self.cpu_params)
 125