3 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
5 from litex
.soc
.interconnect
import wishbone
as wb
6 from litex
.soc
.cores
.cpu
import CPU
8 CPU_VARIANTS
= ["standard", "standard32", "ls180"]
11 def make_wb_bus(prefix
, obj
):
13 for o
in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
14 res
['o_%s_%s' % (prefix
, o
)] = getattr(obj
, o
)
15 for i
in ['ack', 'err', 'dat_r']:
16 res
['i_%s_%s' % (prefix
, i
)] = getattr(obj
, i
)
19 def make_wb_slave(prefix
, obj
):
21 for i
in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
22 res
['i_%s_%s' % (prefix
, i
)] = getattr(obj
, i
)
23 for o
in ['ack', 'err', 'dat_r']:
24 res
['o_%s_%s' % (prefix
, o
)] = getattr(obj
, o
)
30 human_name
= "Libre-SoC"
31 variants
= CPU_VARIANTS
33 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu")
34 linker_output_format
= "elf64-powerpcle"
36 io_regions
= {0xc0000000: 0x10000000} # origin, length
40 return {"csr": 0xc0000000}
45 flags
+= "-mabi=elfv2 "
46 flags
+= "-msoft-float "
47 flags
+= "-mno-string "
48 flags
+= "-mno-multiple "
50 flags
+= "-mno-altivec "
51 flags
+= "-mlittle-endian "
52 flags
+= "-mstrict-align "
53 flags
+= "-fno-stack-protector "
54 flags
+= "-mcmodel=small "
55 flags
+= "-D__microwatt__ "
58 def __init__(self
, platform
, variant
="standard"):
59 self
.platform
= platform
60 self
.variant
= variant
62 self
.interrupt
= Signal(16)
64 if variant
== "standard32":
66 self
.dbus
= dbus
= wb
.Interface(data_width
=32, adr_width
=30)
68 self
.dbus
= dbus
= wb
.Interface(data_width
=64, adr_width
=29)
70 self
.ibus
= ibus
= wb
.Interface(data_width
=64, adr_width
=29)
72 self
.xics_icp
= icp
= wb
.Interface(data_width
=32, adr_width
=30)
73 self
.xics_ics
= ics
= wb
.Interface(data_width
=32, adr_width
=30)
75 if variant
!= "ls180":
76 self
.simple_gpio
= gpio
= wb
.Interface(data_width
=32, adr_width
=30)
78 self
.jtag_wb
= jtag_wb
= wb
.Interface(data_width
=64, adr_width
=29)
80 self
.periph_buses
= [ibus
, dbus
]
81 self
.memory_buses
= []
83 if variant
== "ls180":
84 self
.periph_buses
.append(jtag_wb
)
85 self
.jtag_tck
= Signal(1)
86 self
.jtag_tms
= Signal(1)
87 self
.jtag_tdi
= Signal(1)
88 self
.jtag_tdo
= Signal(1)
90 self
.dmi_addr
= Signal(4)
91 self
.dmi_din
= Signal(64)
92 self
.dmi_dout
= Signal(64)
93 self
.dmi_wr
= Signal(1)
94 self
.dmi_ack
= Signal(1)
95 self
.dmi_req
= Signal(1)
99 self
.cpu_params
= dict(
101 i_clk
= ClockSignal(),
102 i_rst
= ResetSignal() | self
.reset
,
104 # Monitoring / Debugging
107 i_core_bigendian_i
= 0, # Signal(),
108 o_busy_o
= Signal(), # not connected
109 o_memerr_o
= Signal(), # not connected
110 o_pc_o
= Signal(64), # not connected
113 i_int_level_i
= self
.interrupt
,
117 if variant
!= "ls180":
118 self
.cpu_params
.update(dict(
120 i_dmi_addr_i
= self
.dmi_addr
,
121 i_dmi_din
= self
.dmi_din
,
122 o_dmi_dout
= self
.dmi_dout
,
123 i_dmi_req_i
= self
.dmi_req
,
124 i_dmi_we_i
= self
.dmi_wr
,
125 o_dmi_ack_o
= self
.dmi_ack
,
128 self
.cpu_params
.update(dict(
130 o_TAP_bus__tdo
= self
.jtag_tdo
,
131 i_TAP_bus__tdi
= self
.jtag_tdi
,
132 i_TAP_bus__tms
= self
.jtag_tms
,
133 i_TAP_bus__tck
= self
.jtag_tck
,
136 # add wishbone buses to cpu params
137 self
.cpu_params
.update(make_wb_bus("ibus_", ibus
))
138 self
.cpu_params
.update(make_wb_bus("dbus_", dbus
))
139 self
.cpu_params
.update(make_wb_slave("ics_wb_", ics
))
140 self
.cpu_params
.update(make_wb_slave("icp_wb_", icp
))
141 if variant
!= "ls180":
142 self
.cpu_params
.update(make_wb_slave("gpio_wb_", gpio
))
144 self
.cpu_params
.update(make_wb_bus("jtag_wb", jtag_wb
))
146 # add verilog sources
147 self
.add_sources(platform
)
149 def set_reset_address(self
, reset_address
):
150 assert not hasattr(self
, "reset_address")
151 self
.reset_address
= reset_address
152 assert reset_address
== 0x00000000
155 def add_sources(platform
):
156 cdir
= os
.path
.dirname(__file__
)
157 platform
.add_source(os
.path
.join(cdir
, "libresoc.v"))
159 def do_finalize(self
):
160 self
.specials
+= Instance("test_issuer", **self
.cpu_params
)