src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone
   6 from litex.soc.cores.cpu import CPU
   7
   8 CPU_VARIANTS = ["standard", "standard32"]
   9
  10
  11 class LibreSoC(CPU):
  12     name                 = "libre_soc"
  13     human_name           = "Libre-SoC"
  14     variants             = CPU_VARIANTS
  15     endianness           = "little"
  16     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  17     linker_output_format = "elf64-powerpcle"
  18     nop                  = "nop"
  19     io_regions           = {0xc0000000: 0x10000000} # origin, length
  20
  21     @property
  22     def mem_map(self):
  23         return {"csr": 0xc0000000}
  24
  25     @property
  26     def gcc_flags(self):
  27         flags  = "-m64 "
  28         flags += "-mabi=elfv2 "
  29         flags += "-msoft-float "
  30         flags += "-mno-string "
  31         flags += "-mno-multiple "
  32         flags += "-mno-vsx "
  33         flags += "-mno-altivec "
  34         flags += "-mlittle-endian "
  35         flags += "-mstrict-align "
  36         flags += "-fno-stack-protector "
  37         flags += "-mcmodel=small "
  38         flags += "-D__microwatt__ "
  39         return flags
  40
  41     def __init__(self, platform, variant="standard"):
  42         self.platform     = platform
  43         self.variant      = variant
  44         self.reset        = Signal()
  45
  46
  47         if variant == "standard32":
  48             self.data_width           = 32
  49             self.dbus = dbus = wishbone.Interface(data_width=32, adr_width=30)
  50         else:
  51             self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
  52             self.data_width           = 64
  53         self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
  54
  55         self.periph_buses = [ibus, dbus]
  56         self.memory_buses = []
  57
  58         self.dmi_addr = Signal(3)
  59         self.dmi_din = Signal(64)
  60         self.dmi_dout = Signal(64)
  61         self.dmi_wr = Signal(1)
  62         self.dmi_ack = Signal(1)
  63         self.dmi_req = Signal(1)
  64
  65         # # #
  66
  67         self.cpu_params = dict(
  68             # Clock / Reset
  69             i_clk              = ClockSignal(),
  70             i_rst              = ResetSignal() | self.reset,
  71
  72             # IBus
  73             o_ibus__stb        = ibus.stb,
  74             o_ibus__cyc        = ibus.cyc,
  75             o_ibus__cti        = ibus.cti,
  76             o_ibus__bte        = ibus.bte,
  77             o_ibus__we         = ibus.we,
  78             o_ibus__adr        = Cat(ibus.adr), # bytes to words addressing
  79             o_ibus__dat_w      = ibus.dat_w,
  80             o_ibus__sel        = ibus.sel,
  81             i_ibus__ack        = ibus.ack,
  82             i_ibus__err        = ibus.err,
  83             i_ibus__dat_r      = ibus.dat_r,
  84
  85             # DBus
  86             o_dbus__stb        = dbus.stb,
  87             o_dbus__cyc        = dbus.cyc,
  88             o_dbus__cti        = dbus.cti,
  89             o_dbus__bte        = dbus.bte,
  90             o_dbus__we         = dbus.we,
  91             o_dbus__adr        = Cat(dbus.adr), # bytes to words addressing
  92             o_dbus__dat_w      = dbus.dat_w,
  93             o_dbus__sel        = dbus.sel,
  94             i_dbus__ack        = dbus.ack,
  95             i_dbus__err        = dbus.err,
  96             i_dbus__dat_r      = dbus.dat_r,
  97
  98             # Monitoring / Debugging
  99             i_pc_i             = 0,
 100             i_pc_i_ok          = 0,
 101             i_core_bigendian_i = 0, # Signal(),
 102             o_busy_o           = Signal(),
 103             o_memerr_o         = Signal(),
 104
 105             # Debug bus
 106             i_dmi_addr_i          = self.dmi_addr,
 107             i_dmi_din             = self.dmi_din,
 108             o_dmi_dout            = self.dmi_dout,
 109             i_dmi_req_i           = self.dmi_req,
 110             i_dmi_we_i            = self.dmi_wr,
 111             o_dmi_ack_o           = self.dmi_ack,
 112         )
 113
 114         # add verilog sources
 115         self.add_sources(platform)
 116
 117     def set_reset_address(self, reset_address):
 118         assert not hasattr(self, "reset_address")
 119         self.reset_address = reset_address
 120         assert reset_address == 0x00000000
 121
 122     @staticmethod
 123     def add_sources(platform):
 124         cdir = os.path.dirname(__file__)
 125         platform.add_source(os.path.join(cdir, "libresoc.v"))
 126
 127     def do_finalize(self):
 128         self.specials += Instance("test_issuer", **self.cpu_params)
 129