3eb6adc547d54cedc6cc8194e1c27afebf67cc0f
2 # This file is part of LiteX.
4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
5 # SPDX-License-Identifier: BSD-2-Clause
9 conceptually similar to the following:
11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
15 Fits in a JEDEC QFP-100
19 from migen
.fhdl
.structure
import _Fragment
20 from litex
.build
.generic_platform
import (GenericPlatform
, Pins
,
21 Subsignal
, IOStandard
, Misc
,
26 def make_uart(name
, num
):
28 Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
29 Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
32 def make_gpio(name
, num
, n_gpio
):
34 for i
in range(n_gpio
):
35 pins
.append("X%d" % i
)
38 Subsignal("i", Pins(pins
), Misc("PULLMODE=UP")),
39 Subsignal("o", Pins(pins
), Misc("PULLMODE=UP")),
40 Subsignal("oe", Pins(pins
), Misc("PULLMODE=UP")),
41 IOStandard("LVCMOS33"))
45 # IOs ---------------------------------------------------------------------
50 ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
51 ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
52 ("sys_clksel_i", 0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
53 ("sys_pll_48_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
57 Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
58 Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
59 Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
60 Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
65 Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
66 Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
67 Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
68 Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
73 Subsignal("clk", Pins("J1")),
74 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
75 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
76 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
77 Misc("SLEWRATE=FAST"),
78 IOStandard("LVCMOS33"),
83 Subsignal("clk", Pins("J1")),
84 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
85 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
86 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
87 Misc("SLEWRATE=FAST"),
88 IOStandard("LVCMOS33"),
93 Subsignal("clk", Pins("J1")),
94 Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")),
95 Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")),
96 Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")),
97 Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
98 Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
99 Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
100 Misc("SLEWRATE=FAST"),
101 IOStandard("LVCMOS33"),
105 ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
108 "M20 M19 L20 L19 K20 K19 K18 J20",
109 "J19 H20 N19 G20 G19")),
110 Subsignal("dq_i", Pins(
111 "J16 L18 M18 N18 P18 T18 T17 U20",
112 "E19 D20 D19 C20 E18 F18 J18 J17")),
113 Subsignal("dq_o", Pins(
114 "J16 L18 M18 N18 P18 T18 T17 U20",
115 "E19 D20 D19 C20 E18 F18 J18 J17")),
116 Subsignal("dq_oe", Pins("J17")),
117 Subsignal("we_n", Pins("T20")),
118 Subsignal("ras_n", Pins("R20")),
119 Subsignal("cas_n", Pins("T19")),
120 Subsignal("cs_n", Pins("P30")),
121 Subsignal("cke", Pins("F21")),
122 Subsignal("ba", Pins("P19 N20")),
123 Subsignal("dm", Pins("U19 E20")),
124 IOStandard("LVCMOS33"),
125 Misc("SLEWRATE=FAST"),
129 ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")),
130 ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
136 _io
.append( make_gpio("gpio", 0, n_gpio
) )
139 _io
.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
142 _io
.append(make_uart("uart", 0))
144 _io
.append(make_uart("uart", 1))
146 # not connected - eurgh have to adjust this to match the total pincount.
148 nc
= ' '.join("NC%d" % i
for i
in range(num_nc
))
149 _io
.append(("nc", 0, Pins(nc
), IOStandard("LVCMOS33")))
153 # Platform ----------------------------------------------------------------
155 class LS180Platform(GenericPlatform
):
156 default_clk_name
= "sys_clk"
157 default_clk_period
= 1e9
/50e6
159 def __init__(self
, device
="LS180", **kwargs
):
160 assert device
in ["LS180"]
161 GenericPlatform
.__init
__(self
, device
, io(), **kwargs
)
163 def build(self
, fragment
,
172 # Create build directory
173 os
.makedirs(build_dir
, exist_ok
=True)
178 if not isinstance(fragment
, _Fragment
):
179 fragment
= fragment
.get_fragment()
180 platform
.finalize(fragment
)
183 v_output
= platform
.get_verilog(fragment
, name
=build_name
, **kwargs
)
184 named_sc
, named_pc
= platform
.resolve_signals(v_output
.ns
)
185 v_file
= build_name
+ ".v"
186 v_output
.write(v_file
)
187 platform
.add_source(v_file
)
193 def do_finalize(self
, fragment
):
194 super().do_finalize(fragment
)
196 self
.add_period_constraint(self
.lookup_request("clk", loose
=True),