significant reorg of the litex pinspecs to use pinmux JSON files
[soc.git] / src / soc / litex / florent / libresoc / ls180.py
1 #
2 # This file is part of LiteX.
3 #
4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
5 # SPDX-License-Identifier: BSD-2-Clause
6
7 """ls180 ASIC platform
8
9 conceptually similar to the following:
10
11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
13
14 Total I/O pins: 84.
15 Fits in a JEDEC QFP-100
16
17 """
18
19 from migen.fhdl.structure import _Fragment
20 from litex.build.generic_platform import (GenericPlatform, Pins,
21 Subsignal, IOStandard, Misc,
22 )
23 import os
24
25
26 def make_uart(name, num):
27 return (name, num,
28 Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
29 Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
30 )
31
32 def make_gpio(name, num, n_gpio):
33 pins = []
34 for i in range(n_gpio):
35 pins.append("X%d" % i)
36 pins = ' '.join(pins)
37 return (name, 0,
38 Subsignal("i", Pins(pins), Misc("PULLMODE=UP")),
39 Subsignal("o", Pins(pins), Misc("PULLMODE=UP")),
40 Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")),
41 IOStandard("LVCMOS33"))
42
43
44
45 # IOs ---------------------------------------------------------------------
46
47 def io():
48 _io = [
49 # CLK/RST: 2 pins
50 ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
51 ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
52 ("sys_clksel_i", 0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
53 ("sys_pll_48_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
54
55 # JTAG0: 4 pins
56 ("jtag", 0,
57 Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
58 Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
59 Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
60 Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
61 ),
62
63 # I2C0: 2 pins
64 ("i2c", 0,
65 Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
66 Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
67 Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
68 Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
69 ),
70
71 # SPI0: 4 pins
72 ("spimaster", 0,
73 Subsignal("clk", Pins("J1")),
74 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
75 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
76 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
77 Misc("SLEWRATE=FAST"),
78 IOStandard("LVCMOS33"),
79 ),
80
81 # SPICARD0: 4 pins
82 ("spisdcard", 0,
83 Subsignal("clk", Pins("J1")),
84 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
85 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
86 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
87 Misc("SLEWRATE=FAST"),
88 IOStandard("LVCMOS33"),
89 ),
90
91 # SDCARD0: 6 pins
92 ("sdcard", 0,
93 Subsignal("clk", Pins("J1")),
94 Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")),
95 Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")),
96 Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")),
97 Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
98 Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
99 Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
100 Misc("SLEWRATE=FAST"),
101 IOStandard("LVCMOS33"),
102 ),
103
104 # SDRAM: 39 pins
105 ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
106 ("sdram", 0,
107 Subsignal("a", Pins(
108 "M20 M19 L20 L19 K20 K19 K18 J20",
109 "J19 H20 N19 G20 G19")),
110 Subsignal("dq_i", Pins(
111 "J16 L18 M18 N18 P18 T18 T17 U20",
112 "E19 D20 D19 C20 E18 F18 J18 J17")),
113 Subsignal("dq_o", Pins(
114 "J16 L18 M18 N18 P18 T18 T17 U20",
115 "E19 D20 D19 C20 E18 F18 J18 J17")),
116 Subsignal("dq_oe", Pins("J17")),
117 Subsignal("we_n", Pins("T20")),
118 Subsignal("ras_n", Pins("R20")),
119 Subsignal("cas_n", Pins("T19")),
120 Subsignal("cs_n", Pins("P30")),
121 Subsignal("cke", Pins("F21")),
122 Subsignal("ba", Pins("P19 N20")),
123 Subsignal("dm", Pins("U19 E20")),
124 IOStandard("LVCMOS33"),
125 Misc("SLEWRATE=FAST"),
126 ),
127
128 # PWM: 2 pins
129 ("pwm", 0, Pins("P1 P2"), IOStandard("LVCMOS33")),
130 ]
131
132 n_gpio = 16
133
134 # 16 GPIOs
135 _io.append( make_gpio("gpio", 0, n_gpio) )
136
137 # EINT: 3 pins
138 _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
139
140 # UART0: 2 pins
141 _io.append(make_uart("uart", 0))
142 # UART1: 2 pins
143 _io.append(make_uart("uart", 1))
144
145 # not connected - eurgh have to adjust this to match the total pincount.
146 num_nc = 36
147 nc = ' '.join("NC%d" % i for i in range(num_nc))
148 _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
149
150 return _io
151
152 # Platform ----------------------------------------------------------------
153
154 class LS180Platform(GenericPlatform):
155 default_clk_name = "sys_clk"
156 default_clk_period = 1e9/50e6
157
158 def __init__(self, device="LS180", **kwargs):
159 assert device in ["LS180"]
160 GenericPlatform.__init__(self, device, io(), **kwargs)
161
162 def build(self, fragment,
163 build_dir = "build",
164 build_name = "top",
165 run = True,
166 timingstrict = True,
167 **kwargs):
168
169 platform = self
170
171 # Create build directory
172 os.makedirs(build_dir, exist_ok=True)
173 cwd = os.getcwd()
174 os.chdir(build_dir)
175
176 # Finalize design
177 if not isinstance(fragment, _Fragment):
178 fragment = fragment.get_fragment()
179 platform.finalize(fragment)
180
181 # Generate verilog
182 v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
183 named_sc, named_pc = platform.resolve_signals(v_output.ns)
184 v_file = build_name + ".v"
185 v_output.write(v_file)
186 platform.add_source(v_file)
187
188 os.chdir(cwd)
189
190 return v_output.ns
191
192 def do_finalize(self, fragment):
193 super().do_finalize(fragment)
194 return
195 self.add_period_constraint(self.lookup_request("clk", loose=True),
196 1e9/50e6)