2 # This file is part of LiteX.
4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
5 # SPDX-License-Identifier: BSD-2-Clause
9 conceptually similar to the following:
11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
15 Fits in a JEDEC QFP-100
19 from migen
.fhdl
.structure
import _Fragment
20 from litex
.build
.generic_platform
import (GenericPlatform
, Pins
,
21 Subsignal
, IOStandard
, Misc
,
23 from libresoc
.ls180io
import make_uart
, make_gpio
27 def make_uart(name
, num
):
29 Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
30 Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
33 def make_gpio(name
, num
, n_gpio
):
35 for i
in range(n_gpio
):
36 pins
.append("X%d" % i
)
39 Subsignal("i", Pins(pins
), Misc("PULLMODE=UP")),
40 Subsignal("o", Pins(pins
), Misc("PULLMODE=UP")),
41 Subsignal("oe", Pins(pins
), Misc("PULLMODE=UP")),
42 IOStandard("LVCMOS33"))
46 # IOs ---------------------------------------------------------------------
51 ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
52 ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
53 ("sys_clksel_i", 0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
54 ("sys_pll_48_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
58 Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
59 Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
60 Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
61 Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
66 Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
67 Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
68 Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
69 Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
74 Subsignal("clk", Pins("J1")),
75 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
76 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
77 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
78 Misc("SLEWRATE=FAST"),
79 IOStandard("LVCMOS33"),
84 Subsignal("clk", Pins("J1")),
85 Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
86 Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
87 Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
88 Misc("SLEWRATE=FAST"),
89 IOStandard("LVCMOS33"),
94 Subsignal("clk", Pins("J1")),
95 Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")),
96 Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")),
97 Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")),
98 Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
99 Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
100 Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
101 Misc("SLEWRATE=FAST"),
102 IOStandard("LVCMOS33"),
106 ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
109 "M20 M19 L20 L19 K20 K19 K18 J20",
110 "J19 H20 N19 G20 G19")),
111 Subsignal("dq_i", Pins(
112 "J16 L18 M18 N18 P18 T18 T17 U20",
113 "E19 D20 D19 C20 E18 F18 J18 J17")),
114 Subsignal("dq_o", Pins(
115 "J16 L18 M18 N18 P18 T18 T17 U20",
116 "E19 D20 D19 C20 E18 F18 J18 J17")),
117 Subsignal("dq_oe", Pins("J17")),
118 Subsignal("we_n", Pins("T20")),
119 Subsignal("ras_n", Pins("R20")),
120 Subsignal("cas_n", Pins("T19")),
121 Subsignal("cs_n", Pins("P30")),
122 Subsignal("cke", Pins("F21")),
123 Subsignal("ba", Pins("P19 N20")),
124 Subsignal("dm", Pins("U19 E20")),
125 IOStandard("LVCMOS33"),
126 Misc("SLEWRATE=FAST"),
130 ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")),
131 ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
137 _io
.append( make_gpio("gpio", 0, n_gpio
) )
140 _io
.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
143 _io
.append(make_uart("uart", 0))
145 _io
.append(make_uart("uart", 1))
147 # not connected - eurgh have to adjust this to match the total pincount.
149 nc
= ' '.join("NC%d" % i
for i
in range(num_nc
))
150 _io
.append(("nc", 0, Pins(nc
), IOStandard("LVCMOS33")))
154 # Platform ----------------------------------------------------------------
156 class LS180Platform(GenericPlatform
):
157 default_clk_name
= "sys_clk"
158 default_clk_period
= 1e9
/50e6
160 def __init__(self
, device
="LS180", **kwargs
):
161 assert device
in ["LS180"]
162 GenericPlatform
.__init
__(self
, device
, io(), **kwargs
)
164 def build(self
, fragment
,
173 # Create build directory
174 os
.makedirs(build_dir
, exist_ok
=True)
179 if not isinstance(fragment
, _Fragment
):
180 fragment
= fragment
.get_fragment()
181 platform
.finalize(fragment
)
184 v_output
= platform
.get_verilog(fragment
, name
=build_name
, **kwargs
)
185 named_sc
, named_pc
= platform
.resolve_signals(v_output
.ns
)
186 v_file
= build_name
+ ".v"
187 v_output
.write(v_file
)
188 platform
.add_source(v_file
)
194 def do_finalize(self
, fragment
):
195 super().do_finalize(fragment
)
197 self
.add_period_constraint(self
.lookup_request("clk", loose
=True),