src/soc/litex/florent/versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 import litex_boards.targets.versa_ecp5 as versa_ecp5
   7 import litex_boards.targets.ulx3s as ulx3s
   8
   9 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  10                                              soc_sdram_argdict)
  11 from litex.soc.integration.builder import (Builder, builder_args,
  12                                            builder_argdict)
  13
  14 from libresoc import LibreSoC
  15 #from microwatt import Microwatt
  16
  17 # TestSoC
  18 # ----------------------------------------------------------------------------
  19
  20 from litex.build.generic_platform import Subsignal, Pins, IOStandard
  21
  22 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
  23     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  24         kwargs["integrated_rom_size"] = 0x10000
  25         #kwargs["integrated_main_ram_size"] = 0x1000
  26         kwargs["csr_data_width"] = 32
  27         kwargs["l2_size"] = 0
  28         #bus_data_width = 16,
  29
  30         versa_ecp5.BaseSoC.__init__(self,
  31             sys_clk_freq = sys_clk_freq,
  32             cpu_type     = "external",
  33             cpu_cls      = LibreSoC,
  34             cpu_variant = "standardjtagnoirq",
  35             #cpu_cls      = Microwatt,
  36             device       = "LFE5UM",
  37             **kwargs)
  38
  39         # (thanks to daveshah for this tip)
  40         # use platform.add_extension to first define the pins
  41         # https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134
  42
  43         # define the pins, add as an extension, *then* request it
  44         jtag_ios = [
  45             ("jtag", 0,
  46                 Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS33")),
  47                 Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
  48                 Subsignal("tck", Pins("B9"), IOStandard("LVCMOS33")),
  49                 Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
  50             )
  51         ]
  52         self.platform.add_extension(jtag_ios)
  53         jtag = self.platform.request("jtag")
  54
  55         # wire the pins up to CPU JTAG
  56         self.comb += self.cpu.jtag_tck.eq(jtag.tck)
  57         self.comb += self.cpu.jtag_tms.eq(jtag.tms)
  58         self.comb += self.cpu.jtag_tdi.eq(jtag.tdi)
  59         self.comb += jtag.tdo.eq(self.cpu.jtag_tdo)
  60
  61
  62         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  63         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  64         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  65
  66         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  67         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  68         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  69
  70
  71 class ULX3S85FTestSoC(ulx3s.BaseSoC):
  72     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  73         kwargs["integrated_rom_size"] = 0x10000
  74         #kwargs["integrated_main_ram_size"] = 0x1000
  75         kwargs["csr_data_width"] = 32
  76         kwargs["l2_size"] = 0
  77         #bus_data_width = 16,
  78
  79         ulx3s.BaseSoC.__init__(self,
  80             sys_clk_freq = sys_clk_freq,
  81             cpu_type     = "external",
  82             cpu_cls      = LibreSoC,
  83             cpu_variant  = "standardjtag",
  84             #cpu_cls      = Microwatt,
  85             device       = "LFE5U-85F",
  86             **kwargs)
  87
  88         # get 4 arbitrarily assinged logical pins, each gpio has
  89         # 2 distinct physical single non-differential pins p and n
  90         gpio0    = self.platform.request("gpio", 0)
  91         gpio1    = self.platform.request("gpio", 1)
  92
  93         # assign p, n litex 'subsignals' of each gpio to jtag pins
  94         jtag_tdi = gpio0.n
  95         jtag_tms = gpio0.p
  96         jtag_tck = gpio1.n
  97         jtag_tdo = gpio1.p
  98
  99         # wire the pins up to CPU JTAG
 100         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 101         self.comb += self.cpu.jtag_tms.eq(jtag_tms)
 102         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 103         self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
 104
 105 # Build
 106 # ----------------------------------------------------------------------------
 107
 108 def main():
 109     parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
 110                                      "CPU on Versa ECP5 or ULX3S LFE5U85F")
 111     parser.add_argument("--build", action="store_true", help="Build bitstream")
 112     parser.add_argument("--load", action="store_true", help="Load bitstream")
 113     parser.add_argument("--sys-clk-freq",  default=int(16e6),
 114                         help="System clock frequency (default=16MHz)")
 115     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
 116                         "to build for/load to")
 117
 118     builder_args(parser)
 119     soc_sdram_args(parser)
 120     args = parser.parse_args()
 121
 122     if args.fpga == "versa_ecp5":
 123         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 124                                **soc_sdram_argdict(args))
 125
 126     elif args.fpga == "ulx3s85f":
 127         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 128                               **soc_sdram_argdict(args))
 129
 130     else:
 131         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 132                                **soc_sdram_argdict(args))
 133
 134     builder = Builder(soc, **builder_argdict(args))
 135     builder.build(run=args.build)
 136
 137     if args.load:
 138         prog = soc.platform.create_programmer()
 139         prog.load_bitstream(os.path.join(builder.gateware_dir,
 140                                          soc.build_name + ".svf"))
 141
 142 if __name__ == "__main__":
 143     main()