src/soc/litex/florent/versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 from litex_boards.platforms import versa_ecp5
   7 from litex_boards.targets.versa_ecp5 import _CRG, BaseSoC
   8
   9 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  10                                              soc_sdram_argdict)
  11 from litex.soc.integration.builder import (Builder, builder_args,
  12                                            builder_argdict)
  13
  14 from libresoc import LibreSoC
  15 #from microwatt import Microwatt
  16
  17 # TestSoC ------------------------------------------------------------------------------------------
  18
  19 class TestSoC(BaseSoC):
  20     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  21         kwargs["integrated_rom_size"] = 0x10000
  22         #kwargs["integrated_main_ram_size"] = 0x1000
  23         kwargs["csr_data_width"] = 32
  24         kwargs["l2_size"] = 0
  25         #bus_data_width = 16,
  26         BaseSoC.__init__(self, sys_clk_freq,
  27             cpu_type = "external",
  28             cpu_cls  = LibreSoC,
  29             cpu_variant = "standardjtag",
  30             #cpu_cls  = Microwatt,
  31             device        = "LFE5UM",
  32             **kwargs)
  33
  34         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  35         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  36         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  37
  38         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  39         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  40         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  41
  42 # Build --------------------------------------------------------------------------------------------
  43
  44 def main():
  45     parser = argparse.ArgumentParser(
  46                       description="LiteX SoC with LibreSoC CPU on Versa ECP5")
  47     parser.add_argument("--build", action="store_true", help="Build bitstream")
  48     parser.add_argument("--load",  action="store_true", help="Load bitstream")
  49     parser.add_argument("--sys-clk-freq",  default=int(16e6),
  50                          help="System clock frequency (default=16MHz)")
  51
  52     builder_args(parser)
  53     soc_sdram_args(parser)
  54     args = parser.parse_args()
  55
  56     soc = TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
  57                   **soc_sdram_argdict(args))
  58     builder = Builder(soc, **builder_argdict(args))
  59     builder.build(run=args.build)
  60
  61     if args.load:
  62         prog = soc.platform.create_programmer()
  63         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
  64
  65 if __name__ == "__main__":
  66     main()