bd565b0b8b00d2234f9791f4fd975241f15c4059
[soc.git] / src / soc / litex / florent / versa_ecp5.py
1 #!/usr/bin/env python3
2
3 import os
4 import argparse
5
6 import litex_boards.targets.versa_ecp5 as versa_ecp5
7 import litex_boards.targets.ulx3s as ulx3s
8
9 from litex.soc.integration.soc_sdram import (soc_sdram_args,
10 soc_sdram_argdict)
11 from litex.soc.integration.builder import (Builder, builder_args,
12 builder_argdict)
13
14 from libresoc import LibreSoC
15 #from microwatt import Microwatt
16
17 # TestSoC
18 # ----------------------------------------------------------------------------
19
20 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
21 def __init__(self, sys_clk_freq=int(16e6), **kwargs):
22 kwargs["integrated_rom_size"] = 0x10000
23 #kwargs["integrated_main_ram_size"] = 0x1000
24 kwargs["csr_data_width"] = 32
25 kwargs["l2_size"] = 0
26 #bus_data_width = 16,
27
28 versa_ecp5.BaseSoC.__init__(self,
29 sys_clk_freq = sys_clk_freq,
30 cpu_type = "external",
31 cpu_cls = LibreSoC,
32 cpu_variant = "standardjtagnoirq",
33 #cpu_cls = Microwatt,
34 device = "LFE5UM",
35 **kwargs)
36
37 #self.add_constant("MEMTEST_BUS_SIZE", 256//16)
38 #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
39 #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
40
41 #self.add_constant("MEMTEST_BUS_DEBUG", 1)
42 #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
43 #self.add_constant("MEMTEST_DATA_DEBUG", 1)
44
45 class ULX3S85FTestSoC(ulx3s.BaseSoC):
46 def __init__(self, sys_clk_freq=int(16e6), **kwargs):
47 kwargs["integrated_rom_size"] = 0x10000
48 #kwargs["integrated_main_ram_size"] = 0x1000
49 kwargs["csr_data_width"] = 32
50 kwargs["l2_size"] = 0
51 #bus_data_width = 16,
52
53 ulx3s.BaseSoC.__init__(self,
54 sys_clk_freq = sys_clk_freq,
55 cpu_type = "external",
56 cpu_cls = LibreSoC,
57 cpu_variant = "standardjtag",
58 #cpu_cls = Microwatt,
59 device = "LFE5U-85F",
60 **kwargs)
61
62 # Build
63 # ----------------------------------------------------------------------------
64
65 def main():
66 parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
67 "CPU on Versa ECP5 or ULX3S LFE5U85F")
68 parser.add_argument("--build", action="store_true", help="Build bitstream")
69 parser.add_argument("--load", action="store_true", help="Load bitstream")
70 parser.add_argument("--sys-clk-freq", default=int(16e6),
71 help="System clock frequency (default=16MHz)")
72 parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
73 "to build for/load to")
74
75 builder_args(parser)
76 soc_sdram_args(parser)
77 args = parser.parse_args()
78
79 if args.fpga == "versa_ecp5":
80 soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
81 **soc_sdram_argdict(args))
82
83 elif args.fpga == "ulx3s85f":
84 soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
85 **soc_sdram_argdict(args))
86
87 else:
88 soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
89 **soc_sdram_argdict(args))
90
91 builder = Builder(soc, **builder_argdict(args))
92 builder.build(run=args.build)
93
94 if args.load:
95 prog = soc.platform.create_programmer()
96 prog.load_bitstream(os.path.join(builder.gateware_dir,
97 soc.build_name + ".svf"))
98
99 if __name__ == "__main__":
100 main()