6 import litex_boards
.targets
.versa_ecp5
as versa_ecp5
7 import litex_boards
.targets
.ulx3s
as ulx3s
9 from litex
.soc
.integration
.soc_sdram
import (soc_sdram_args
,
11 from litex
.soc
.integration
.builder
import (Builder
, builder_args
,
14 from libresoc
import LibreSoC
15 #from microwatt import Microwatt
18 # ----------------------------------------------------------------------------
20 class VersaECP5TestSoC(versa_ecp5
.BaseSoC
):
21 def __init__(self
, sys_clk_freq
=int(16e6
), **kwargs
):
22 kwargs
["integrated_rom_size"] = 0x10000
23 #kwargs["integrated_main_ram_size"] = 0x1000
24 kwargs
["csr_data_width"] = 32
28 versa_ecp5
.BaseSoC
.__init
__(self
,
29 sys_clk_freq
= sys_clk_freq
,
30 cpu_type
= "external",
32 cpu_variant
= "standardjtagnoirq",
37 #self.add_constant("MEMTEST_BUS_SIZE", 256//16)
38 #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
39 #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
41 #self.add_constant("MEMTEST_BUS_DEBUG", 1)
42 #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
43 #self.add_constant("MEMTEST_DATA_DEBUG", 1)
45 class ULX3S85FTestSoC(ulx3s
.BaseSoC
):
46 def __init__(self
, sys_clk_freq
=int(16e6
), **kwargs
):
47 kwargs
["integrated_rom_size"] = 0x10000
48 #kwargs["integrated_main_ram_size"] = 0x1000
49 kwargs
["csr_data_width"] = 32
53 ulx3s
.BaseSoC
.__init
__(self
,
54 sys_clk_freq
= sys_clk_freq
,
55 cpu_type
= "external",
57 cpu_variant
= "standardjtag",
63 # ----------------------------------------------------------------------------
66 parser
= argparse
.ArgumentParser(description
="LiteX SoC with LibreSoC " \
67 "CPU on Versa ECP5 or ULX3S LFE5U85F")
68 parser
.add_argument("--build", action
="store_true", help="Build bitstream")
69 parser
.add_argument("--load", action
="store_true", help="Load bitstream")
70 parser
.add_argument("--sys-clk-freq", default
=int(16e6
),
71 help="System clock frequency (default=16MHz)")
72 parser
.add_argument("--fpga", default
="versa_ecp5", help="FPGA target " \
73 "to build for/load to")
76 soc_sdram_args(parser
)
77 args
= parser
.parse_args()
79 if args
.fpga
== "versa_ecp5":
80 soc
= VersaECP5TestSoC(sys_clk_freq
=int(float(args
.sys_clk_freq
)),
81 **soc_sdram_argdict(args
))
83 elif args
.fpga
== "ulx3s85f":
84 soc
= ULX3S85FTestSoC(sys_clk_freq
=int(float(args
.sys_clk_freq
)),
85 **soc_sdram_argdict(args
))
88 soc
= VersaECP5TestSoC(sys_clk_freq
=int(float(args
.sys_clk_freq
)),
89 **soc_sdram_argdict(args
))
91 builder
= Builder(soc
, **builder_argdict(args
))
92 builder
.build(run
=args
.build
)
95 prog
= soc
.platform
.create_programmer()
96 prog
.load_bitstream(os
.path
.join(builder
.gateware_dir
,
97 soc
.build_name
+ ".svf"))
99 if __name__
== "__main__":