src/soc/litex/florent/versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 import litex_boards.targets.versa_ecp5 as versa_ecp5
   7 import litex_boards.targets.ulx3s as ulx3s
   8
   9 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  10                                              soc_sdram_argdict)
  11 from litex.soc.integration.builder import (Builder, builder_args,
  12                                            builder_argdict)
  13
  14 from libresoc import LibreSoC
  15 #from microwatt import Microwatt
  16
  17 # TestSoC
  18 # ----------------------------------------------------------------------------
  19
  20 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
  21     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  22         kwargs["integrated_rom_size"] = 0x10000
  23         #kwargs["integrated_main_ram_size"] = 0x1000
  24         kwargs["csr_data_width"] = 32
  25         kwargs["l2_size"] = 0
  26         #bus_data_width = 16,
  27
  28         versa_ecp5.BaseSoC.__init__(self,
  29             sys_clk_freq = sys_clk_freq,
  30             cpu_type     = "external",
  31             cpu_cls      = LibreSoC,
  32             cpu_variant  = "standardjtag",
  33             cpu_variant = "standardjtagnoirq",
  34             #cpu_cls      = Microwatt,
  35             device       = "LFE5UM",
  36             **kwargs)
  37
  38         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  39         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  40         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  41
  42         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  43         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  44         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  45
  46 class ULX3S85FTestSoC(ulx3s.BaseSoC):
  47     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  48         kwargs["integrated_rom_size"] = 0x10000
  49         #kwargs["integrated_main_ram_size"] = 0x1000
  50         kwargs["csr_data_width"] = 32
  51         kwargs["l2_size"] = 0
  52         #bus_data_width = 16,
  53
  54         ulx3s.BaseSoC.__init__(self,
  55             sys_clk_freq = sys_clk_freq,
  56             cpu_type     = "external",
  57             cpu_cls      = LibreSoC,
  58             cpu_variant  = "standardjtag",
  59             #cpu_cls      = Microwatt,
  60             device       = "LFE5U-85F",
  61             **kwargs)
  62
  63 # Build
  64 # ----------------------------------------------------------------------------
  65
  66 def main():
  67     parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
  68                                      "CPU on Versa ECP5 or ULX3S LFE5U85F")
  69     parser.add_argument("--build", action="store_true", help="Build bitstream")
  70     parser.add_argument("--load", action="store_true", help="Load bitstream")
  71     parser.add_argument("--sys-clk-freq",  default=int(16e6),
  72                         help="System clock frequency (default=16MHz)")
  73     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
  74                         "to build for/load to")
  75
  76     builder_args(parser)
  77     soc_sdram_args(parser)
  78     args = parser.parse_args()
  79
  80     if args.fpga == "versa_ecp5":
  81         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
  82                                **soc_sdram_argdict(args))
  83
  84     elif args.fpga == "ulx3s85f":
  85         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
  86                               **soc_sdram_argdict(args))
  87
  88     else:
  89         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
  90                                **soc_sdram_argdict(args))
  91
  92     builder = Builder(soc, **builder_argdict(args))
  93     builder.build(run=args.build)
  94
  95     if args.load:
  96         prog = soc.platform.create_programmer()
  97         prog.load_bitstream(os.path.join(builder.gateware_dir,
  98                                          soc.build_name + ".svf"))
  99
 100 if __name__ == "__main__":
 101     main()