1 from nmigen
.back
import rtlil
2 from nmigen
.back
.pysim
import Simulator
, Delay
4 from .config
import MemoryPipeConfig
5 from .l1_cache_memory
import L1CacheMemory
8 class TestL1CacheMemory(unittest
.TestCase
):
9 def test_l1_cache_memory(self
):
10 config
= MemoryPipeConfig(bytes_per_cache_line
=4,
13 base_name
= "test_l1_cache_memory"
14 with self
.subTest(part
="synthesize"):
15 dut
= L1CacheMemory(config
)
16 vl
= rtlil
.convert(dut
)
17 with
open(f
"{base_name}.il", "w") as f
:
19 dut
= L1CacheMemory(config
)
22 sim
.add_clock(clock_period
)
25 for set_index
in range(config
.l1_set_count
):
26 for way_index
in range(config
.l1_way_count
):
27 yield dut
.set_index
.eq(set_index
)
28 yield dut
.way_index
.eq(way_index
)
29 yield dut
.write_enable
.eq(1)
30 yield dut
.write_byte_en
.eq(0xF)
31 write_data
= set_index
* 0x10 + way_index
32 write_data
*= 0x00010001
33 write_data ^
= 0x80808080
34 yield dut
.write_data
.eq(write_data
)
36 yield dut
.set_index
.eq(set_index
)
37 yield dut
.way_index
.eq(way_index
)
38 yield dut
.write_enable
.eq(0)
40 yield Delay(clock_period
/ 10)
41 yield dut
.set_index
.eq(set_index
+ 1)
42 yield dut
.way_index
.eq(way_index
+ 1)
43 yield Delay(clock_period
/ 10)
44 read_data
= (yield dut
.read_data
)
45 self
.assertEqual(read_data
, write_data
)
47 sim
.add_sync_process(process
)
48 with sim
.write_vcd(vcd_file
=open(f
"{base_name}.vcd", "w"),
49 gtkw_file
=open(f
"{base_name}.gtkw", "w")):