src/soc/minerva/units/debug/top.py

   1 from nmigen import Elaboratable, Module, Signal, Record
   2
   3
   4 from ...csr import AutoCSR, CSR
   5 from ...wishbone import wishbone_layout
   6 from .controller import DebugController
   7 from .jtag import JTAGReg, dtmcs_layout, dmi_layout, jtag_layout
   8 from .regfile import DebugRegisterFile
   9 from .wbmaster import wishbone_layout, DebugWishboneMaster
  10
  11 from jtagtap import JTAGTap
  12
  13 __all__ = ["DebugUnit"]
  14
  15
  16 jtag_regs = {
  17     JTAGReg.IDCODE: [("value", 32)],
  18     JTAGReg.DTMCS:  dtmcs_layout,
  19     JTAGReg.DMI:    dmi_layout
  20 }
  21
  22
  23 class DebugUnit(Elaboratable, AutoCSR):
  24     def __init__(self):
  25         self.jtag = Record(jtag_layout)
  26         self.dbus = Record(wishbone_layout)
  27
  28         self.trigger_haltreq = Signal()
  29
  30         self.x_ebreak = Signal()
  31         self.x_pc = Signal(32)
  32         self.x_stall = Signal()
  33
  34         self.m_branch_taken = Signal()
  35         self.m_branch_target = Signal(32)
  36         self.m_mret = Signal()
  37         self.m_exception = Signal()
  38         self.m_pc = Signal(32)
  39         self.m_valid = Signal()
  40         self.mepc_r_base = Signal(30)
  41         self.mtvec_r_base = Signal(30)
  42
  43         self.dcsr_step = Signal()
  44         self.dcsr_ebreakm = Signal()
  45         self.dpc_value = Signal(32)
  46
  47         self.halt = Signal()
  48         self.halted = Signal()
  49         self.killall = Signal()
  50         self.resumereq = Signal()
  51         self.resumeack = Signal()
  52
  53         self.dbus_busy = Signal()
  54
  55         self.csrf_addr = Signal(12)
  56         self.csrf_re = Signal()
  57         self.csrf_dat_r = Signal(32)
  58         self.csrf_we = Signal()
  59         self.csrf_dat_w = Signal(32)
  60
  61         self.gprf_addr = Signal(5)
  62         self.gprf_re = Signal()
  63         self.gprf_dat_r = Signal(32)
  64         self.gprf_we = Signal()
  65         self.gprf_dat_w = Signal(32)
  66
  67     def elaborate(self, platform):
  68         m = Module()
  69
  70         tap        = m.submodules.tap        = JTAGTap(jtag_regs)
  71         regfile    = m.submodules.regfile    = DebugRegisterFile(tap.regs[JTAGReg.DMI])
  72         controller = m.submodules.controller = DebugController(regfile)
  73         wbmaster   = m.submodules.wbmaster   = DebugWishboneMaster(regfile)
  74
  75         m.d.comb += [
  76             tap.port.connect(self.jtag),
  77             tap.regs[JTAGReg.IDCODE].r.eq(0x10e31913), # Usurpate a Spike core for now.
  78             tap.regs[JTAGReg.DTMCS].r.eq(0x61) # (abits=6, version=1) TODO
  79         ]
  80
  81         m.d.comb += [
  82             controller.trigger_haltreq.eq(self.trigger_haltreq),
  83
  84             controller.x_ebreak.eq(self.x_ebreak),
  85             controller.x_pc.eq(self.x_pc),
  86             controller.x_stall.eq(self.x_stall),
  87
  88             controller.m_branch_taken.eq(self.m_branch_taken),
  89             controller.m_branch_target.eq(self.m_branch_target),
  90             controller.m_pc.eq(self.m_pc),
  91             controller.m_valid.eq(self.m_valid),
  92
  93             self.halt.eq(controller.halt),
  94             controller.halted.eq(self.halted),
  95             self.killall.eq(controller.killall),
  96             self.resumereq.eq(controller.resumereq),
  97             controller.resumeack.eq(self.resumeack),
  98
  99             self.dcsr_step.eq(controller.dcsr.r.step),
 100             self.dcsr_ebreakm.eq(controller.dcsr.r.ebreakm),
 101             self.dpc_value.eq(controller.dpc.r.value),
 102
 103             self.csrf_addr.eq(controller.csrf_addr),
 104             self.csrf_re.eq(controller.csrf_re),
 105             controller.csrf_dat_r.eq(self.csrf_dat_r),
 106             self.csrf_we.eq(controller.csrf_we),
 107             self.csrf_dat_w.eq(controller.csrf_dat_w),
 108
 109             self.gprf_addr.eq(controller.gprf_addr),
 110             self.gprf_re.eq(controller.gprf_re),
 111             controller.gprf_dat_r.eq(self.gprf_dat_r),
 112             self.gprf_we.eq(controller.gprf_we),
 113             self.gprf_dat_w.eq(controller.gprf_dat_w),
 114         ]
 115
 116         m.d.comb += [
 117             wbmaster.bus.connect(self.dbus),
 118             self.dbus_busy.eq(wbmaster.dbus_busy)
 119         ]
 120
 121         return m