1 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Const
, Mux
2 from nmigen
.utils
import log2_int
4 from ..cache
import L1Cache
5 from ..wishbone
import wishbone_layout
, WishboneArbiter
, Cycle
8 __all__
= ["PCSelector", "FetchUnitInterface", "BareFetchUnit",
12 class PCSelector(Elaboratable
):
14 self
.f_pc
= Signal(32)
15 self
.d_pc
= Signal(32)
16 self
.d_branch_predict_taken
= Signal()
17 self
.d_branch_target
= Signal(32)
18 self
.d_valid
= Signal()
19 self
.x_pc
= Signal(32)
20 self
.x_fence_i
= Signal()
21 self
.x_valid
= Signal()
22 self
.m_branch_predict_taken
= Signal()
23 self
.m_branch_taken
= Signal()
24 self
.m_branch_target
= Signal(32)
25 self
.m_exception
= Signal()
26 self
.m_mret
= Signal()
27 self
.m_valid
= Signal()
28 self
.mtvec_r_base
= Signal(30)
29 self
.mepc_r_base
= Signal(30)
31 self
.a_pc
= Signal(32)
33 def elaborate(self
, platform
):
36 with m
.If(self
.m_exception
& self
.m_valid
):
37 m
.d
.comb
+= self
.a_pc
.eq(self
.mtvec_r_base
<< 2)
38 with m
.Elif(self
.m_mret
& self
.m_valid
):
39 m
.d
.comb
+= self
.a_pc
.eq(self
.mepc_r_base
<< 2)
40 with m
.Elif(self
.m_branch_predict_taken
& ~self
.m_branch_taken
&
42 m
.d
.comb
+= self
.a_pc
.eq(self
.x_pc
)
43 with m
.Elif(~self
.m_branch_predict_taken
& self
.m_branch_taken
&
45 m
.d
.comb
+= self
.a_pc
.eq(self
.m_branch_target
),
46 with m
.Elif(self
.x_fence_i
& self
.x_valid
):
47 m
.d
.comb
+= self
.a_pc
.eq(self
.d_pc
)
48 with m
.Elif(self
.d_branch_predict_taken
& self
.d_valid
):
49 m
.d
.comb
+= self
.a_pc
.eq(self
.d_branch_target
),
51 m
.d
.comb
+= self
.a_pc
.eq(self
.f_pc
+ 4)
56 class FetchUnitInterface
:
58 self
.ibus
= Record(wishbone_layout
)
60 self
.a_pc
= Signal(32)
61 self
.a_stall
= Signal()
62 self
.a_valid
= Signal()
63 self
.f_stall
= Signal()
64 self
.f_valid
= Signal()
66 self
.a_busy
= Signal()
67 self
.f_busy
= Signal()
68 self
.f_instruction
= Signal(32)
69 self
.f_fetch_error
= Signal()
70 self
.f_badaddr
= Signal(30)
73 class BareFetchUnit(FetchUnitInterface
, Elaboratable
):
74 def elaborate(self
, platform
):
77 ibus_rdata
= Signal
.like(self
.ibus
.dat_r
)
78 with m
.If(self
.ibus
.cyc
):
79 with m
.If(self
.ibus
.ack | self
.ibus
.err | ~self
.f_valid
):
83 ibus_rdata
.eq(self
.ibus
.dat_r
)
85 with m
.Elif(self
.a_valid
& ~self
.a_stall
):
87 self
.ibus
.adr
.eq(self
.a_pc
[2:]),
92 with m
.If(self
.ibus
.cyc
& self
.ibus
.err
):
94 self
.f_fetch_error
.eq(1),
95 self
.f_badaddr
.eq(self
.ibus
.adr
)
97 with m
.Elif(~self
.f_stall
):
98 m
.d
.sync
+= self
.f_fetch_error
.eq(0)
100 m
.d
.comb
+= self
.a_busy
.eq(self
.ibus
.cyc
)
102 with m
.If(self
.f_fetch_error
):
105 self
.f_instruction
.eq(0x00000013) # nop (addi x0, x0, 0)
109 self
.f_busy
.eq(self
.ibus
.cyc
),
110 self
.f_instruction
.eq(ibus_rdata
)
116 class CachedFetchUnit(FetchUnitInterface
, Elaboratable
):
117 def __init__(self
, *icache_args
):
120 self
.icache_args
= icache_args
122 self
.a_flush
= Signal()
123 self
.f_pc
= Signal(32)
125 def elaborate(self
, platform
):
128 icache
= m
.submodules
.icache
= L1Cache(*self
.icache_args
)
130 a_icache_select
= Signal()
131 f_icache_select
= Signal()
133 m
.d
.comb
+= a_icache_select
.eq((self
.a_pc
>= icache
.base
) & (self
.a_pc
< icache
.limit
))
134 with m
.If(~self
.a_stall
):
135 m
.d
.sync
+= f_icache_select
.eq(a_icache_select
)
138 icache
.s1_addr
.eq(self
.a_pc
[2:]),
139 icache
.s1_flush
.eq(self
.a_flush
),
140 icache
.s1_stall
.eq(self
.a_stall
),
141 icache
.s1_valid
.eq(self
.a_valid
& a_icache_select
),
142 icache
.s2_addr
.eq(self
.f_pc
[2:]),
143 icache
.s2_re
.eq(Const(1)),
144 icache
.s2_evict
.eq(Const(0)),
145 icache
.s2_valid
.eq(self
.f_valid
& f_icache_select
)
148 ibus_arbiter
= m
.submodules
.ibus_arbiter
= WishboneArbiter()
149 m
.d
.comb
+= ibus_arbiter
.bus
.connect(self
.ibus
)
151 icache_pt
= ibus_arbiter
.port(priority
=0)
153 icache_pt
.cyc
.eq(icache
.bus_re
),
154 icache_pt
.stb
.eq(icache
.bus_re
),
155 icache_pt
.adr
.eq(icache
.bus_addr
),
156 icache_pt
.cti
.eq(Mux(icache
.bus_last
, Cycle
.END
, Cycle
.INCREMENT
)),
157 icache_pt
.bte
.eq(Const(log2_int(icache
.nwords
) - 1)),
158 icache
.bus_valid
.eq(icache_pt
.ack
),
159 icache
.bus_error
.eq(icache_pt
.err
),
160 icache
.bus_rdata
.eq(icache_pt
.dat_r
)
163 bare_port
= ibus_arbiter
.port(priority
=1)
164 bare_rdata
= Signal
.like(bare_port
.dat_r
)
165 with m
.If(bare_port
.cyc
):
166 with m
.If(bare_port
.ack | bare_port
.err | ~self
.f_valid
):
170 bare_rdata
.eq(bare_port
.dat_r
)
172 with m
.Elif(~a_icache_select
& self
.a_valid
& ~self
.a_stall
):
176 bare_port
.adr
.eq(self
.a_pc
[2:])
179 with m
.If(self
.ibus
.cyc
& self
.ibus
.err
):
181 self
.f_fetch_error
.eq(1),
182 self
.f_badaddr
.eq(self
.ibus
.adr
)
184 with m
.Elif(~self
.f_stall
):
185 m
.d
.sync
+= self
.f_fetch_error
.eq(0)
187 with m
.If(a_icache_select
):
188 m
.d
.comb
+= self
.a_busy
.eq(0)
190 m
.d
.comb
+= self
.a_busy
.eq(bare_port
.cyc
)
192 with m
.If(self
.f_fetch_error
):
195 self
.f_instruction
.eq(0x00000013) # nop (addi x0, x0, 0)
197 with m
.Elif(f_icache_select
):
199 self
.f_busy
.eq(icache
.s2_re
& icache
.s2_miss
),
200 self
.f_instruction
.eq(icache
.s2_rdata
)
204 self
.f_busy
.eq(bare_port
.cyc
),
205 self
.f_instruction
.eq(bare_rdata
)