1 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Cat
, Const
, Mux
2 from nmigen
.utils
import log2_int
3 from nmigen
.lib
.fifo
import SyncFIFO
5 from soc
.minerva
.cache
import L1Cache
6 from soc
.minerva
.wishbone
import wishbone_layout
, WishboneArbiter
, Cycle
9 __all__
= ["LoadStoreUnitInterface", "BareLoadStoreUnit",
10 "CachedLoadStoreUnit"]
13 class LoadStoreUnitInterface
:
14 def __init__(self
, addr_wid
=32, mask_wid
=4, data_wid
=32):
15 self
.dbus
= Record(wishbone_layout
)
16 badwid
= addr_wid
-log2_int(mask_wid
) # TODO: is this correct?
19 self
.x_addr
= Signal(addr_wid
) # The address used for loads/stores
20 self
.x_mask
= Signal(mask_wid
) # Mask of which bytes to write
21 self
.x_load
= Signal() # set to do a memory load
22 self
.x_store
= Signal() # set to do a memory store
23 self
.x_store_data
= Signal(data_wid
) # The data to write when storing
24 self
.x_stall
= Signal() # do nothing until low
25 self
.x_valid
= Signal() # Not entirely sure yet
26 self
.m_stall
= Signal() # do nothing until low
27 self
.m_valid
= Signal() # Not entirely sure yet
30 self
.x_busy
= Signal() # set when the memory is busy
31 self
.m_busy
= Signal() # set when the memory is busy
32 self
.m_load_data
= Signal(data_wid
) # Data returned from a memory read
33 # Data validity is NOT indicated by m_valid or x_valid as
34 # those are inputs. I believe it is valid on the next cycle
35 # after raising m_load where busy is low
37 self
.m_load_error
= Signal() # Whether there was an error when loading
38 self
.m_store_error
= Signal() # Whether there was an error when storing
39 self
.m_badaddr
= Signal(badwid
) # The address of the load/store error
42 class BareLoadStoreUnit(LoadStoreUnitInterface
, Elaboratable
):
43 def elaborate(self
, platform
):
46 with m
.If(self
.dbus
.cyc
):
47 with m
.If(self
.dbus
.ack | self
.dbus
.err | ~self
.m_valid
):
51 self
.m_load_data
.eq(self
.dbus
.dat_r
)
53 with m
.Elif((self
.x_load | self
.x_store
) &
54 self
.x_valid
& ~self
.x_stall
):
58 self
.dbus
.adr
.eq(self
.x_addr
[2:]),
59 self
.dbus
.sel
.eq(self
.x_mask
),
60 self
.dbus
.we
.eq(self
.x_store
),
61 self
.dbus
.dat_w
.eq(self
.x_store_data
)
64 with m
.If(self
.dbus
.cyc
& self
.dbus
.err
):
66 self
.m_load_error
.eq(~self
.dbus
.we
),
67 self
.m_store_error
.eq(self
.dbus
.we
),
68 self
.m_badaddr
.eq(self
.dbus
.adr
)
70 with m
.Elif(~self
.m_stall
):
72 self
.m_load_error
.eq(0),
73 self
.m_store_error
.eq(0)
76 m
.d
.comb
+= self
.x_busy
.eq(self
.dbus
.cyc
)
78 with m
.If(self
.m_load_error | self
.m_store_error
):
79 m
.d
.comb
+= self
.m_busy
.eq(0)
81 m
.d
.comb
+= self
.m_busy
.eq(self
.dbus
.cyc
)
86 class CachedLoadStoreUnit(LoadStoreUnitInterface
, Elaboratable
):
87 def __init__(self
, *dcache_args
):
90 self
.dcache_args
= dcache_args
92 self
.x_fence_i
= Signal()
93 self
.x_flush
= Signal()
94 self
.m_addr
= Signal(32)
95 self
.m_load
= Signal()
96 self
.m_store
= Signal()
98 def elaborate(self
, platform
):
101 dcache
= m
.submodules
.dcache
= L1Cache(*self
.dcache_args
)
103 x_dcache_select
= Signal()
104 m_dcache_select
= Signal()
106 m
.d
.comb
+= x_dcache_select
.eq((self
.x_addr
>= dcache
.base
) &
107 (self
.x_addr
< dcache
.limit
))
108 with m
.If(~self
.x_stall
):
109 m
.d
.sync
+= m_dcache_select
.eq(x_dcache_select
)
112 dcache
.s1_addr
.eq(self
.x_addr
[2:]),
113 dcache
.s1_flush
.eq(self
.x_flush
),
114 dcache
.s1_stall
.eq(self
.x_stall
),
115 dcache
.s1_valid
.eq(self
.x_valid
& x_dcache_select
),
116 dcache
.s2_addr
.eq(self
.m_addr
[2:]),
117 dcache
.s2_re
.eq(self
.m_load
),
118 dcache
.s2_evict
.eq(self
.m_store
),
119 dcache
.s2_valid
.eq(self
.m_valid
& m_dcache_select
)
122 wrbuf_w_data
= Record([("addr", 30), ("mask", 4), ("data", 32)])
123 wrbuf_r_data
= Record
.like(wrbuf_w_data
)
124 wrbuf
= m
.submodules
.wrbuf
= SyncFIFO(width
=len(wrbuf_w_data
),
127 wrbuf
.w_data
.eq(wrbuf_w_data
),
128 wrbuf_w_data
.addr
.eq(self
.x_addr
[2:]),
129 wrbuf_w_data
.mask
.eq(self
.x_mask
),
130 wrbuf_w_data
.data
.eq(self
.x_store_data
),
131 wrbuf
.w_en
.eq(self
.x_store
& self
.x_valid
&
132 x_dcache_select
& ~self
.x_stall
),
133 wrbuf_r_data
.eq(wrbuf
.r_data
),
136 dbus_arbiter
= m
.submodules
.dbus_arbiter
= WishboneArbiter()
137 m
.d
.comb
+= dbus_arbiter
.bus
.connect(self
.dbus
)
139 wrbuf_port
= dbus_arbiter
.port(priority
=0)
140 with m
.If(wrbuf_port
.cyc
):
141 with m
.If(wrbuf_port
.ack | wrbuf_port
.err
):
143 wrbuf_port
.cyc
.eq(0),
146 m
.d
.comb
+= wrbuf
.r_en
.eq(1)
147 with m
.Elif(wrbuf
.r_rdy
):
149 wrbuf_port
.cyc
.eq(1),
150 wrbuf_port
.stb
.eq(1),
151 wrbuf_port
.adr
.eq(wrbuf_r_data
.addr
),
152 wrbuf_port
.sel
.eq(wrbuf_r_data
.mask
),
153 wrbuf_port
.dat_w
.eq(wrbuf_r_data
.data
)
155 m
.d
.comb
+= wrbuf_port
.we
.eq(Const(1))
157 dcache_port
= dbus_arbiter
.port(priority
=1)
158 cti
= Mux(dcache
.bus_last
, Cycle
.END
, Cycle
.INCREMENT
)
160 dcache_port
.cyc
.eq(dcache
.bus_re
),
161 dcache_port
.stb
.eq(dcache
.bus_re
),
162 dcache_port
.adr
.eq(dcache
.bus_addr
),
163 dcache_port
.cti
.eq(cti
),
164 dcache_port
.bte
.eq(Const(log2_int(dcache
.nwords
) - 1)),
165 dcache
.bus_valid
.eq(dcache_port
.ack
),
166 dcache
.bus_error
.eq(dcache_port
.err
),
167 dcache
.bus_rdata
.eq(dcache_port
.dat_r
)
170 bare_port
= dbus_arbiter
.port(priority
=2)
171 bare_rdata
= Signal
.like(bare_port
.dat_r
)
172 with m
.If(bare_port
.cyc
):
173 with m
.If(bare_port
.ack | bare_port
.err | ~self
.m_valid
):
177 bare_rdata
.eq(bare_port
.dat_r
)
179 with m
.Elif((self
.x_load | self
.x_store
) &
180 ~x_dcache_select
& self
.x_valid
& ~self
.x_stall
):
184 bare_port
.adr
.eq(self
.x_addr
[2:]),
185 bare_port
.sel
.eq(self
.x_mask
),
186 bare_port
.we
.eq(self
.x_store
),
187 bare_port
.dat_w
.eq(self
.x_store_data
)
190 with m
.If(self
.dbus
.cyc
& self
.dbus
.err
):
192 self
.m_load_error
.eq(~self
.dbus
.we
),
193 self
.m_store_error
.eq(self
.dbus
.we
),
194 self
.m_badaddr
.eq(self
.dbus
.adr
)
196 with m
.Elif(~self
.m_stall
):
198 self
.m_load_error
.eq(0),
199 self
.m_store_error
.eq(0)
202 with m
.If(self
.x_fence_i
):
203 m
.d
.comb
+= self
.x_busy
.eq(wrbuf
.r_rdy
)
204 with m
.Elif(x_dcache_select
):
205 m
.d
.comb
+= self
.x_busy
.eq(self
.x_store
& ~wrbuf
.w_rdy
)
207 m
.d
.comb
+= self
.x_busy
.eq(bare_port
.cyc
)
209 with m
.If(self
.m_load_error | self
.m_store_error
):
212 self
.m_load_data
.eq(0)
214 with m
.Elif(m_dcache_select
):
216 self
.m_busy
.eq(dcache
.s2_re
& dcache
.s2_miss
),
217 self
.m_load_data
.eq(dcache
.s2_rdata
)
221 self
.m_busy
.eq(bare_port
.cyc
),
222 self
.m_load_data
.eq(bare_rdata
)