1 from nmigen
import Elaboratable
, Module
, Signal
, Record
, Cat
, Const
, Mux
2 from nmigen
.utils
import log2_int
3 from nmigen
.lib
.fifo
import SyncFIFO
5 from soc
.minerva
.cache
import L1Cache
6 from soc
.minerva
.wishbone
import wishbone_layout
, WishboneArbiter
, Cycle
9 __all__
= ["LoadStoreUnitInterface", "BareLoadStoreUnit",
10 "CachedLoadStoreUnit"]
13 class LoadStoreUnitInterface
:
14 def __init__(self
, addr_wid
=32, mask_wid
=4, data_wid
=32):
15 self
.dbus
= Record(wishbone_layout
)
16 badwid
= addr_wid
-log2_int(mask_wid
) # TODO: is this correct?
19 self
.x_addr
= Signal(addr_wid
) # The address used for loads/stores
20 self
.x_mask
= Signal(mask_wid
) # Mask of which bytes to write
21 self
.x_load
= Signal() # set to do a memory load
22 self
.x_store
= Signal() # set to do a memory store
23 self
.x_store_data
= Signal(data_wid
) # The data to write when storing
24 self
.x_stall
= Signal() # do nothing until low
25 self
.x_valid
= Signal() # Not entirely sure yet
26 self
.m_stall
= Signal() # do nothing until low
27 self
.m_valid
= Signal() # Not entirely sure yet
30 self
.x_busy
= Signal() # set when the memory is busy
31 self
.m_busy
= Signal() # set when the memory is busy
32 self
.m_load_data
= Signal(data_wid
) # Data returned from a memory read
33 self
.m_load_error
= Signal() # Whether there was an error when loading
34 self
.m_store_error
= Signal() # Whether there was an error when storing
35 self
.m_badaddr
= Signal(badwid
) # The address of the load/store error
38 class BareLoadStoreUnit(LoadStoreUnitInterface
, Elaboratable
):
39 def elaborate(self
, platform
):
42 with m
.If(self
.dbus
.cyc
):
43 with m
.If(self
.dbus
.ack | self
.dbus
.err | ~self
.m_valid
):
47 self
.m_load_data
.eq(self
.dbus
.dat_r
)
49 with m
.Elif((self
.x_load | self
.x_store
) &
50 self
.x_valid
& ~self
.x_stall
):
54 self
.dbus
.adr
.eq(self
.x_addr
[2:]),
55 self
.dbus
.sel
.eq(self
.x_mask
),
56 self
.dbus
.we
.eq(self
.x_store
),
57 self
.dbus
.dat_w
.eq(self
.x_store_data
)
60 with m
.If(self
.dbus
.cyc
& self
.dbus
.err
):
62 self
.m_load_error
.eq(~self
.dbus
.we
),
63 self
.m_store_error
.eq(self
.dbus
.we
),
64 self
.m_badaddr
.eq(self
.dbus
.adr
)
66 with m
.Elif(~self
.m_stall
):
68 self
.m_load_error
.eq(0),
69 self
.m_store_error
.eq(0)
72 m
.d
.comb
+= self
.x_busy
.eq(self
.dbus
.cyc
)
74 with m
.If(self
.m_load_error | self
.m_store_error
):
75 m
.d
.comb
+= self
.m_busy
.eq(0)
77 m
.d
.comb
+= self
.m_busy
.eq(self
.dbus
.cyc
)
82 class CachedLoadStoreUnit(LoadStoreUnitInterface
, Elaboratable
):
83 def __init__(self
, *dcache_args
):
86 self
.dcache_args
= dcache_args
88 self
.x_fence_i
= Signal()
89 self
.x_flush
= Signal()
90 self
.m_addr
= Signal(32)
91 self
.m_load
= Signal()
92 self
.m_store
= Signal()
94 def elaborate(self
, platform
):
97 dcache
= m
.submodules
.dcache
= L1Cache(*self
.dcache_args
)
99 x_dcache_select
= Signal()
100 m_dcache_select
= Signal()
102 m
.d
.comb
+= x_dcache_select
.eq((self
.x_addr
>= dcache
.base
) &
103 (self
.x_addr
< dcache
.limit
))
104 with m
.If(~self
.x_stall
):
105 m
.d
.sync
+= m_dcache_select
.eq(x_dcache_select
)
108 dcache
.s1_addr
.eq(self
.x_addr
[2:]),
109 dcache
.s1_flush
.eq(self
.x_flush
),
110 dcache
.s1_stall
.eq(self
.x_stall
),
111 dcache
.s1_valid
.eq(self
.x_valid
& x_dcache_select
),
112 dcache
.s2_addr
.eq(self
.m_addr
[2:]),
113 dcache
.s2_re
.eq(self
.m_load
),
114 dcache
.s2_evict
.eq(self
.m_store
),
115 dcache
.s2_valid
.eq(self
.m_valid
& m_dcache_select
)
118 wrbuf_w_data
= Record([("addr", 30), ("mask", 4), ("data", 32)])
119 wrbuf_r_data
= Record
.like(wrbuf_w_data
)
120 wrbuf
= m
.submodules
.wrbuf
= SyncFIFO(width
=len(wrbuf_w_data
),
123 wrbuf
.w_data
.eq(wrbuf_w_data
),
124 wrbuf_w_data
.addr
.eq(self
.x_addr
[2:]),
125 wrbuf_w_data
.mask
.eq(self
.x_mask
),
126 wrbuf_w_data
.data
.eq(self
.x_store_data
),
127 wrbuf
.w_en
.eq(self
.x_store
& self
.x_valid
&
128 x_dcache_select
& ~self
.x_stall
),
129 wrbuf_r_data
.eq(wrbuf
.r_data
),
132 dbus_arbiter
= m
.submodules
.dbus_arbiter
= WishboneArbiter()
133 m
.d
.comb
+= dbus_arbiter
.bus
.connect(self
.dbus
)
135 wrbuf_port
= dbus_arbiter
.port(priority
=0)
136 with m
.If(wrbuf_port
.cyc
):
137 with m
.If(wrbuf_port
.ack | wrbuf_port
.err
):
139 wrbuf_port
.cyc
.eq(0),
142 m
.d
.comb
+= wrbuf
.r_en
.eq(1)
143 with m
.Elif(wrbuf
.r_rdy
):
145 wrbuf_port
.cyc
.eq(1),
146 wrbuf_port
.stb
.eq(1),
147 wrbuf_port
.adr
.eq(wrbuf_r_data
.addr
),
148 wrbuf_port
.sel
.eq(wrbuf_r_data
.mask
),
149 wrbuf_port
.dat_w
.eq(wrbuf_r_data
.data
)
151 m
.d
.comb
+= wrbuf_port
.we
.eq(Const(1))
153 dcache_port
= dbus_arbiter
.port(priority
=1)
154 cti
= Mux(dcache
.bus_last
, Cycle
.END
, Cycle
.INCREMENT
)
156 dcache_port
.cyc
.eq(dcache
.bus_re
),
157 dcache_port
.stb
.eq(dcache
.bus_re
),
158 dcache_port
.adr
.eq(dcache
.bus_addr
),
159 dcache_port
.cti
.eq(cti
),
160 dcache_port
.bte
.eq(Const(log2_int(dcache
.nwords
) - 1)),
161 dcache
.bus_valid
.eq(dcache_port
.ack
),
162 dcache
.bus_error
.eq(dcache_port
.err
),
163 dcache
.bus_rdata
.eq(dcache_port
.dat_r
)
166 bare_port
= dbus_arbiter
.port(priority
=2)
167 bare_rdata
= Signal
.like(bare_port
.dat_r
)
168 with m
.If(bare_port
.cyc
):
169 with m
.If(bare_port
.ack | bare_port
.err | ~self
.m_valid
):
173 bare_rdata
.eq(bare_port
.dat_r
)
175 with m
.Elif((self
.x_load | self
.x_store
) &
176 ~x_dcache_select
& self
.x_valid
& ~self
.x_stall
):
180 bare_port
.adr
.eq(self
.x_addr
[2:]),
181 bare_port
.sel
.eq(self
.x_mask
),
182 bare_port
.we
.eq(self
.x_store
),
183 bare_port
.dat_w
.eq(self
.x_store_data
)
186 with m
.If(self
.dbus
.cyc
& self
.dbus
.err
):
188 self
.m_load_error
.eq(~self
.dbus
.we
),
189 self
.m_store_error
.eq(self
.dbus
.we
),
190 self
.m_badaddr
.eq(self
.dbus
.adr
)
192 with m
.Elif(~self
.m_stall
):
194 self
.m_load_error
.eq(0),
195 self
.m_store_error
.eq(0)
198 with m
.If(self
.x_fence_i
):
199 m
.d
.comb
+= self
.x_busy
.eq(wrbuf
.r_rdy
)
200 with m
.Elif(x_dcache_select
):
201 m
.d
.comb
+= self
.x_busy
.eq(self
.x_store
& ~wrbuf
.w_rdy
)
203 m
.d
.comb
+= self
.x_busy
.eq(bare_port
.cyc
)
205 with m
.If(self
.m_load_error | self
.m_store_error
):
208 self
.m_load_data
.eq(0)
210 with m
.Elif(m_dcache_select
):
212 self
.m_busy
.eq(dcache
.s2_re
& dcache
.s2_miss
),
213 self
.m_load_data
.eq(dcache
.s2_rdata
)
217 self
.m_busy
.eq(bare_port
.cyc
),
218 self
.m_load_data
.eq(bare_rdata
)