src/soc/pipe/logical/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.alu.pipe_data import IntegerData
   4
   5
   6 class ALUInputData(IntegerData):
   7     def __init__(self, pspec):
   8         super().__init__(pspec)
   9         self.a = Signal(64, reset_less=True) # RA
  10         self.b = Signal(64, reset_less=True) # RB/immediate
  11         self.so = Signal(reset_less=True)
  12         self.carry_in = Signal(reset_less=True)
  13
  14     def __iter__(self):
  15         yield from super().__iter__()
  16         yield self.a
  17         yield self.b
  18         yield self.carry_in
  19         yield self.so
  20
  21     def eq(self, i):
  22         lst = super().eq(i)
  23         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  24                       self.carry_in.eq(i.carry_in),
  25                       self.so.eq(i.so)]