src/soc/pipe/shift_rot/formal/proof_main_stage.py

   1 # Proof of correctness for partitioned equal signal combiner
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3
   4 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
   5                     signed)
   6 from nmigen.asserts import Assert, AnyConst, Assume, Cover
   7 from nmigen.test.utils import FHDLTestCase
   8 from nmigen.cli import rtlil
   9
  10 from soc.shift_rot.main_stage import ShiftRotMainStage
  11 from soc.alu.pipe_data import ALUPipeSpec
  12 from soc.alu.alu_input_record import CompALUOpSubset
  13 from soc.decoder.power_enums import InternalOp
  14 import unittest
  15
  16
  17 # This defines a module to drive the device under test and assert
  18 # properties about its outputs
  19 class Driver(Elaboratable):
  20     def __init__(self):
  21         # inputs and outputs
  22         pass
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27
  28         rec = CompALUOpSubset()
  29         recwidth = 0
  30         # Setup random inputs for dut.op
  31         for p in rec.ports():
  32             width = p.width
  33             recwidth += width
  34             comb += p.eq(AnyConst(width))
  35
  36         pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
  37         m.submodules.dut = dut = ShiftRotMainStage(pspec)
  38
  39         # convenience variables
  40         a = dut.i.rs
  41         b = dut.i.rb
  42         ra = dut.i.ra
  43         carry_in = dut.i.carry_in
  44         so_in = dut.i.so
  45         carry_out = dut.o.carry_out
  46         o = dut.o.o
  47
  48         # setup random inputs
  49         comb += [a.eq(AnyConst(64)),
  50                  b.eq(AnyConst(64)),
  51                  carry_in.eq(AnyConst(1)),
  52                  so_in.eq(AnyConst(1))]
  53
  54         comb += dut.i.ctx.op.eq(rec)
  55
  56         # Assert that op gets copied from the input to output
  57         for rec_sig in rec.ports():
  58             name = rec_sig.name
  59             dut_sig = getattr(dut.o.ctx.op, name)
  60             comb += Assert(dut_sig == rec_sig)
  61
  62         # signed and signed/32 versions of input a
  63         a_signed = Signal(signed(64))
  64         a_signed_32 = Signal(signed(32))
  65         comb += a_signed.eq(a)
  66         comb += a_signed_32.eq(a[0:32])
  67
  68         # main assertion of arithmetic operations
  69         with m.Switch(rec.insn_type):
  70             with m.Case(InternalOp.OP_SHL):
  71                 comb += Assume(ra == 0)
  72                 with m.If(rec.is_32bit):
  73                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
  74                     comb += Assert(o[32:64] == 0)
  75                 with m.Else():
  76                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
  77             with m.Case(InternalOp.OP_SHR):
  78                 comb += Assume(ra == 0)
  79                 with m.If(~rec.is_signed):
  80                     with m.If(rec.is_32bit):
  81                         comb += Assert(o[0:32] == (a[0:32] >> b[0:6]))
  82                         comb += Assert(o[32:64] == 0)
  83                     with m.Else():
  84                         comb += Assert(o == (a >> b[0:7]))
  85                 with m.Else():
  86                     with m.If(rec.is_32bit):
  87                         comb += Assert(o[0:32] == (a_signed_32 >> b[0:6]))
  88                         comb += Assert(o[32:64] == Repl(a[31], 32))
  89                     with m.Else():
  90                         comb += Assert(o == (a_signed >> b[0:7]))
  91
  92         return m
  93
  94
  95 class ALUTestCase(FHDLTestCase):
  96     def test_formal(self):
  97         module = Driver()
  98         self.assertFormal(module, mode="bmc", depth=2)
  99         self.assertFormal(module, mode="cover", depth=2)
 100     def test_ilang(self):
 101         dut = Driver()
 102         vl = rtlil.convert(dut, ports=[])
 103         with open("main_stage.il", "w") as f:
 104             f.write(vl)
 105
 106
 107 if __name__ == '__main__':
 108     unittest.main()