src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile
   7     * SPR regfile
   8     * CR regfile
   9     * XER regfile
  10     * FAST regfile
  11
  12 Links:
  13
  14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  15 * https://libre-soc.org/3d_gpu/architecture/regfile/
  16 * https://libre-soc.org/openpower/isatables/sprs.csv
  17 """
  18
  19 # TODO
  20
  21 from soc.regfile import RegFile, RegFileArray
  22 from soc.decoder.power_enums import SPR
  23
  24
  25 # Integer Regfile
  26 class IntRegs(RegFileArray):
  27     """IntRegs
  28
  29     * QTY 32of 64-bit registers
  30     * 3R1W
  31     * Array-based unary-indexed (not binary-indexed)
  32     * write-through capability (read on same cycle as write)
  33     """
  34     def __init__(self):
  35         super().__init__(64, 32)
  36         self.w_ports = [self.write_port("dest")]
  37         self.r_ports = [self.write_port("src1"),
  38                         self.write_port("src2"),
  39                         self.write_port("src3")]
  40
  41
  42 # CR Regfile
  43 class CRRegs(RegFileArray):
  44     """Condition Code Registers (CR0-7)
  45
  46     * QTY 8of 8-bit registers
  47     * 8R8W (!) with additional 1R1W for the "full" width
  48     * Array-based unary-indexed (not binary-indexed)
  49     * write-through capability (read on same cycle as write)
  50     """
  51     def __init__(self):
  52         super().__init__(4, 8)
  53         self.w_ports = [self.write_port("dest")]
  54         self.r_ports = [self.write_port("src1"),
  55                         self.write_port("src2"),
  56                         self.write_port("src3")]
  57
  58
  59 # SPR Regfile
  60 class SPRRegs(RegFile):
  61     """SPRRegs
  62
  63     * QTY len(SPRs) 64-bit registers
  64     * 1R1W
  65     * binary-indexed but REQUIRES MAPPING
  66     * write-through capability (read on same cycle as write)
  67     """
  68     def __init__(self):
  69         n_sprs = len(SPR)
  70         super().__init__(64, n_sprs)
  71         self.w_ports = [self.write_port("dest")]
  72         self.r_ports = [self.write_port("src")]