src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  11
  12 Note: this should NOT have name conventions hard-coded (dedicated ports per
  13 regname).  However it is convenient for now.
  14
  15 Links:
  16
  17 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  18 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  19 * https://libre-soc.org/3d_gpu/architecture/regfile/
  20 * https://libre-soc.org/openpower/isatables/sprs.csv
  21 """
  22
  23 # TODO
  24
  25 from soc.regfile.regfile import RegFile, RegFileArray
  26 from soc.regfile.virtual_port import VirtualRegPort
  27 from soc.decoder.power_enums import SPR
  28
  29
  30 # Integer Regfile
  31 class IntRegs(RegFileArray):
  32     """IntRegs
  33
  34     * QTY 32of 64-bit registers
  35     * 3R2W
  36     * Array-based unary-indexed (not binary-indexed)
  37     * write-through capability (read on same cycle as write)
  38     """
  39     def __init__(self):
  40         super().__init__(64, 32)
  41         self.w_ports = {'o': self.write_port("dest1"),
  42                         'o1': self.write_port("dest2")} # for now (LD/ST update)
  43         self.r_ports = {'ra': self.read_port("src1"),
  44                         'rb': self.read_port("src2"),
  45                         'rc': self.read_port("src3")}
  46
  47
  48 # Fast SPRs Regfile
  49 class FastRegs(RegFileArray):
  50     """FastRegs
  51
  52     FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  53
  54     * QTY 8of 64-bit registers
  55     * 3R2W
  56     * Array-based unary-indexed (not binary-indexed)
  57     * write-through capability (read on same cycle as write)
  58     """
  59     PC = 0
  60     MSR = 1
  61     CTR = 2
  62     LR = 3
  63     TAR = 4
  64     SRR0 = 5
  65     SRR1 = 6
  66     def __init__(self):
  67         super().__init__(64, 8)
  68         self.w_ports = {'nia': self.write_port("dest1"),
  69                         'msr': self.write_port("dest2"),
  70                         'spr1': self.write_port("dest3"),
  71                         'spr2': self.write_port("dest3")}
  72         self.r_ports = {'cia': self.read_port("src1"),
  73                         'msr': self.read_port("src2"),
  74                         'spr1': self.read_port("src3"),
  75                         'spr2': self.read_port("src3")}
  76
  77
  78 # CR Regfile
  79 class CRRegs(VirtualRegPort):
  80     """Condition Code Registers (CR0-7)
  81
  82     * QTY 8of 8-bit registers
  83     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
  84     * Array-based unary-indexed (not binary-indexed)
  85     * write-through capability (read on same cycle as write)
  86     """
  87     def __init__(self):
  88         super().__init__(32, 8)
  89         self.w_ports = {'full_cr': self.full_wr, # 32-bit (masked, 8-en lines)
  90                         'cr_a': self.write_port("dest1"), # 4-bit, unary-indexed
  91                         'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed
  92         self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
  93                         'cr_a': self.read_port("src1"),
  94                         'cr_b': self.read_port("src2"),
  95                         'cr_c': self.read_port("src3")}
  96
  97
  98 # XER Regfile
  99 class XERRegs(VirtualRegPort):
 100     """XER Registers (SO, CA/CA32, OV/OV32)
 101
 102     * QTY 3of 2-bit registers
 103     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
 104     * Array-based unary-indexed (not binary-indexed)
 105     * write-through capability (read on same cycle as write)
 106     """
 107     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 108     CA=1 # CA and CA32
 109     OV=2 # OV and OV32
 110     def __init__(self):
 111         super().__init__(6, 3)
 112         self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
 113                         'xer_so': self.write_port("dest1"),
 114                         'xer_ca': self.write_port("dest2"),
 115                         'xer_ov': self.write_port("dest3")}
 116         self.r_ports = {'full_xer': self.full_rd, # 6-bit (masked, 3-en lines)
 117                         'xer_so': self.read_port("src1"),
 118                         'xer_ca': self.read_port("src2"),
 119                         'xer_ov': self.read_port("src3")}
 120
 121
 122 # SPR Regfile
 123 class SPRRegs(RegFile):
 124     """SPRRegs
 125
 126     * QTY len(SPRs) 64-bit registers
 127     * 1R1W
 128     * binary-indexed but REQUIRES MAPPING
 129     * write-through capability (read on same cycle as write)
 130     """
 131     def __init__(self):
 132         n_sprs = len(SPR)
 133         super().__init__(64, n_sprs)
 134         self.w_ports = {'spr': self.write_port(name="dest")}
 135         self.r_ports = {'spr': self.read_port("src")}
 136
 137
 138 # class containing all regfiles: int, cr, xer, fast, spr
 139 class RegFiles:
 140     def __init__(self):
 141         self.rf = {}
 142         for (name, kls) in [('int', IntRegs),
 143                             ('cr', CRRegs),
 144                             ('xer', XERRegs),
 145                             ('fast', FastRegs),
 146                             ('spr', SPRRegs),]:
 147             rf = self.rf[name] = kls()
 148             setattr(self, name, rf)
 149
 150     def elaborate_into(self, m, platform):
 151         for (name, rf) in self.rf.items():
 152             setattr(m.submodules, name, rf)
 153         return m
 154