src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  11
  12 Links:
  13
  14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  16 * https://libre-soc.org/3d_gpu/architecture/regfile/
  17 * https://libre-soc.org/openpower/isatables/sprs.csv
  18 """
  19
  20 # TODO
  21
  22 from soc.regfile.regfile import RegFile, RegFileArray
  23 from soc.regfile.virtual_port import VirtualRegPort
  24 from soc.decoder.power_enums import SPR
  25
  26
  27 # Integer Regfile
  28 class IntRegs(RegFileArray):
  29     """IntRegs
  30
  31     * QTY 32of 64-bit registers
  32     * 3R2W
  33     * Array-based unary-indexed (not binary-indexed)
  34     * write-through capability (read on same cycle as write)
  35     """
  36     def __init__(self):
  37         super().__init__(64, 32)
  38         self.w_ports = [self.write_port("dest1"),
  39                         self.write_port("dest2")] # for now (LD/ST update)
  40         self.r_ports = [self.read_port("src1"),
  41                         self.read_port("src2"),
  42                         self.read_port("src3")]
  43
  44
  45 # Fast SPRs Regfile
  46 class FastRegs(RegFileArray):
  47     """FastRegs
  48
  49     FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  50
  51     * QTY 8of 64-bit registers
  52     * 3R2W
  53     * Array-based unary-indexed (not binary-indexed)
  54     * write-through capability (read on same cycle as write)
  55     """
  56     PC = 0
  57     MSR = 1
  58     CTR = 2
  59     LR = 3
  60     TAR = 4
  61     SRR1 = 5
  62     SRR2 = 6
  63     def __init__(self):
  64         super().__init__(64, 8)
  65         self.w_ports = [self.write_port("dest1"),
  66                         self.write_port("dest2")]
  67         self.r_ports = [self.read_port("src1"),
  68                         self.read_port("src2"),
  69                         self.read_port("src3")]
  70
  71
  72 # CR Regfile
  73 class CRRegs(VirtualRegPort):
  74     """Condition Code Registers (CR0-7)
  75
  76     * QTY 8of 8-bit registers
  77     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
  78     * Array-based unary-indexed (not binary-indexed)
  79     * write-through capability (read on same cycle as write)
  80     """
  81     def __init__(self):
  82         super().__init__(32, 8)
  83         self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
  84                         self.write_port("dest")] # 4-bit wide, unary-indexed
  85         self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
  86                         self.read_port("src1"),
  87                         self.read_port("src2"),
  88                         self.read_port("src3")]
  89
  90
  91 # XER Regfile
  92 class XERRegs(VirtualRegPort):
  93     """XER Registers (SO, CA/CA32, OV/OV32)
  94
  95     * QTY 3of 2-bit registers
  96     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
  97     * Array-based unary-indexed (not binary-indexed)
  98     * write-through capability (read on same cycle as write)
  99     """
 100     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 101     CA=1 # CA and CA32
 102     OV=2 # OV and OV32
 103     def __init__(self):
 104         super().__init__(6, 2)
 105         self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
 106                         self.write_port("dest1"),
 107                         self.write_port("dest2"),
 108                         self.write_port("dest3")]
 109         self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
 110                         self.read_port("src1"),
 111                         self.read_port("src2"),
 112                         self.read_port("src3")]
 113
 114
 115 # SPR Regfile
 116 class SPRRegs(RegFile):
 117     """SPRRegs
 118
 119     * QTY len(SPRs) 64-bit registers
 120     * 1R1W
 121     * binary-indexed but REQUIRES MAPPING
 122     * write-through capability (read on same cycle as write)
 123     """
 124     def __init__(self):
 125         n_sprs = len(SPR)
 126         super().__init__(64, n_sprs)
 127         self.w_ports = [self.write_port(name="dest")]
 128         self.r_ports = [self.read_port("src")]
 129
 130
 131 # class containing all regfiles: int, cr, xer, fast, spr
 132 class RegFiles:
 133     def __init__(self):
 134         self.rf = {}
 135         for (name, kls) in [('int', IntRegs),
 136                             ('cr', CRRegs),
 137                             ('xer', XERRegs),
 138                             ('fast', FastRegs),
 139                             ('spr', SPRRegs),]:
 140             rf = self.rf[name] = kls()
 141             setattr(self, name, rf)
 142
 143     def elaborate_into(self, m, platform):
 144         for (name, rf) in self.rf.items():
 145             setattr(m.submodules, name, rf)
 146         return m
 147