src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  11
  12 Note: this should NOT have name conventions hard-coded (dedicated ports per
  13 regname).  However it is convenient for now.
  14
  15 Links:
  16
  17 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  18 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  19 * https://libre-soc.org/3d_gpu/architecture/regfile/
  20 * https://libre-soc.org/openpower/isatables/sprs.csv
  21 """
  22
  23 # TODO
  24
  25 from soc.regfile.regfile import RegFile, RegFileArray
  26 from soc.regfile.virtual_port import VirtualRegPort
  27 from soc.decoder.power_enums import SPR
  28
  29
  30 # Integer Regfile
  31 class IntRegs(RegFileArray):
  32     """IntRegs
  33
  34     * QTY 32of 64-bit registers
  35     * 3R2W
  36     * Array-based unary-indexed (not binary-indexed)
  37     * write-through capability (read on same cycle as write)
  38     """
  39     def __init__(self):
  40         super().__init__(64, 32)
  41         self.w_ports = {'o': self.write_port("dest1"),
  42                         'o1': self.write_port("dest2")} # for now (LD/ST update)
  43         self.r_ports = {'ra': self.read_port("src1"),
  44                         'rb': self.read_port("src2"),
  45                         'rc': self.read_port("src3")}
  46
  47
  48 # Fast SPRs Regfile
  49 class FastRegs(RegFileArray):
  50     """FastRegs
  51
  52     FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  53
  54     * QTY 8of 64-bit registers
  55     * 3R2W
  56     * Array-based unary-indexed (not binary-indexed)
  57     * write-through capability (read on same cycle as write)
  58
  59     Note: d_wr1 and d_rd1 are for use by the decoder, to get at the PC.
  60     will probably have to also add one so it can get at the MSR as well.
  61     """
  62     PC = 0
  63     MSR = 1
  64     CTR = 2
  65     LR = 3
  66     TAR = 4
  67     SRR0 = 5
  68     SRR1 = 6
  69     def __init__(self):
  70         super().__init__(64, 8)
  71         self.w_ports = {'nia': self.write_port("nia"),
  72                         'msr': self.write_port("dest2"),
  73                         'fast1': self.write_port("dest3"),
  74                         'fast2': self.write_port("dest4"),
  75                         'd_wr1': self.write_port("d_wr1")}
  76         self.r_ports = {'cia': self.read_port("src1"),
  77                         'msr': self.read_port("src2"),
  78                         'fast1': self.read_port("src3"),
  79                         'fast2': self.read_port("src4"),
  80                         'd_rd1': self.read_port("d_rd1")}
  81
  82
  83 # CR Regfile
  84 class CRRegs(VirtualRegPort):
  85     """Condition Code Registers (CR0-7)
  86
  87     * QTY 8of 8-bit registers
  88     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
  89     * Array-based unary-indexed (not binary-indexed)
  90     * write-through capability (read on same cycle as write)
  91     """
  92     def __init__(self):
  93         super().__init__(32, 8)
  94         self.w_ports = {'full_cr': self.full_wr, # 32-bit (masked, 8-en lines)
  95                         'cr_a': self.write_port("dest1"), # 4-bit, unary-indexed
  96                         'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed
  97         self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
  98                         'cr_a': self.read_port("src1"),
  99                         'cr_b': self.read_port("src2"),
 100                         'cr_c': self.read_port("src3")}
 101
 102
 103 # XER Regfile
 104 class XERRegs(VirtualRegPort):
 105     """XER Registers (SO, CA/CA32, OV/OV32)
 106
 107     * QTY 3of 2-bit registers
 108     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
 109     * Array-based unary-indexed (not binary-indexed)
 110     * write-through capability (read on same cycle as write)
 111     """
 112     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 113     CA=1 # CA and CA32
 114     OV=2 # OV and OV32
 115     def __init__(self):
 116         super().__init__(6, 3)
 117         self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
 118                         'xer_so': self.write_port("dest1"),
 119                         'xer_ca': self.write_port("dest2"),
 120                         'xer_ov': self.write_port("dest3")}
 121         self.r_ports = {'full_xer': self.full_rd, # 6-bit (masked, 3-en lines)
 122                         'xer_so': self.read_port("src1"),
 123                         'xer_ca': self.read_port("src2"),
 124                         'xer_ov': self.read_port("src3")}
 125
 126
 127 # SPR Regfile
 128 class SPRRegs(RegFile):
 129     """SPRRegs
 130
 131     * QTY len(SPRs) 64-bit registers
 132     * 1R1W
 133     * binary-indexed but REQUIRES MAPPING
 134     * write-through capability (read on same cycle as write)
 135     """
 136     def __init__(self):
 137         n_sprs = len(SPR)
 138         super().__init__(64, n_sprs)
 139         self.w_ports = {'spr': self.write_port(name="dest")}
 140         self.r_ports = {'spr': self.read_port("src")}
 141
 142
 143 # class containing all regfiles: int, cr, xer, fast, spr
 144 class RegFiles:
 145     def __init__(self):
 146         self.rf = {}
 147         for (name, kls) in [('int', IntRegs),
 148                             ('cr', CRRegs),
 149                             ('xer', XERRegs),
 150                             ('fast', FastRegs),
 151                             ('spr', SPRRegs),]:
 152             rf = self.rf[name] = kls()
 153             setattr(self, name, rf)
 154
 155     def elaborate_into(self, m, platform):
 156         for (name, rf) in self.rf.items():
 157             setattr(m.submodules, name, rf)
 158         return m
 159