1 # POWER9 Register Files
4 Defines the following register files:
6 * INT regfile - 32x 64-bit
7 * SPR regfile - 110x 64-bit
9 * XER regfile - XER.so, XER.ca/ca32, XER.ov/ov32
10 * FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2
14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
15 * https://bugs.libre-soc.org/show_bug.cgi?id=351
16 * https://libre-soc.org/3d_gpu/architecture/regfile/
17 * https://libre-soc.org/openpower/isatables/sprs.csv
22 from soc
.regfile
.regfile
import RegFile
, RegFileArray
23 from soc
.regfile
.virtual_port
import VirtualRegPort
24 from soc
.decoder
.power_enums
import SPR
28 class IntRegs(RegFileArray
):
31 * QTY 32of 64-bit registers
33 * Array-based unary-indexed (not binary-indexed)
34 * write-through capability (read on same cycle as write)
37 super().__init
__(64, 32)
38 self
.w_ports
= [self
.write_port("dest1"),
39 self
.write_port("dest2")] # for now (LD/ST update)
40 self
.r_ports
= [self
.read_port("src1"),
41 self
.read_port("src2"),
42 self
.read_port("src3")]
46 class FastRegs(RegFileArray
):
49 FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2
51 * QTY 8of 64-bit registers
53 * Array-based unary-indexed (not binary-indexed)
54 * write-through capability (read on same cycle as write)
64 super().__init
__(64, 8)
65 self
.w_ports
= [self
.write_port("dest1"),
66 self
.write_port("dest2"),
67 self
.write_port("dest3")]
68 self
.r_ports
= [self
.read_port("src1"),
69 self
.read_port("src2"),
70 self
.read_port("src3")]
74 class CRRegs(VirtualRegPort
):
75 """Condition Code Registers (CR0-7)
77 * QTY 8of 8-bit registers
78 * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
79 * Array-based unary-indexed (not binary-indexed)
80 * write-through capability (read on same cycle as write)
83 super().__init
__(32, 8)
84 self
.w_ports
= [self
.full_wr
, # 32-bit wide (masked, 8-en lines)
85 self
.write_port("dest")] # 4-bit wide, unary-indexed
86 self
.r_ports
= [self
.full_rd
, # 32-bit wide (masked, 8-en lines)
87 self
.read_port("src1"),
88 self
.read_port("src2"),
89 self
.read_port("src3")]
93 class XERRegs(VirtualRegPort
):
94 """XER Registers (SO, CA/CA32, OV/OV32)
96 * QTY 3of 2-bit registers
97 * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
98 * Array-based unary-indexed (not binary-indexed)
99 * write-through capability (read on same cycle as write)
101 SO
=0 # this is actually 2-bit but we ignore 1 bit of it
105 super().__init
__(6, 3)
106 self
.w_ports
= [self
.full_wr
, # 6-bit wide (masked, 3-en lines)
107 self
.write_port("dest1"),
108 self
.write_port("dest2"),
109 self
.write_port("dest3")]
110 self
.r_ports
= [self
.full_rd
, # 6-bit wide (masked, 3-en lines)
111 self
.read_port("src1"),
112 self
.read_port("src2"),
113 self
.read_port("src3")]
117 class SPRRegs(RegFile
):
120 * QTY len(SPRs) 64-bit registers
122 * binary-indexed but REQUIRES MAPPING
123 * write-through capability (read on same cycle as write)
127 super().__init
__(64, n_sprs
)
128 self
.w_ports
= [self
.write_port(name
="dest")]
129 self
.r_ports
= [self
.read_port("src")]
132 # class containing all regfiles: int, cr, xer, fast, spr
136 for (name
, kls
) in [('int', IntRegs
),
141 rf
= self
.rf
[name
] = kls()
142 setattr(self
, name
, rf
)
144 def elaborate_into(self
, m
, platform
):
145 for (name
, rf
) in self
.rf
.items():
146 setattr(m
.submodules
, name
, rf
)