src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  11
  12 Links:
  13
  14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  16 * https://libre-soc.org/3d_gpu/architecture/regfile/
  17 * https://libre-soc.org/openpower/isatables/sprs.csv
  18 """
  19
  20 # TODO
  21
  22 from nmigen import Elaboratable, Module
  23 from soc.regfile.regfile import RegFile, RegFileArray
  24 from soc.regfile.virtual_port import VirtualRegPort
  25 from soc.decoder.power_enums import SPR
  26
  27
  28 # Integer Regfile
  29 class IntRegs(RegFileArray):
  30     """IntRegs
  31
  32     * QTY 32of 64-bit registers
  33     * 3R2W
  34     * Array-based unary-indexed (not binary-indexed)
  35     * write-through capability (read on same cycle as write)
  36     """
  37     def __init__(self):
  38         super().__init__(64, 32)
  39         self.w_ports = [self.write_port("dest1"),
  40                         self.write_port("dest2")] # for now (LD/ST update)
  41         self.r_ports = [self.read_port("src1"),
  42                         self.read_port("src2"),
  43                         self.read_port("src3")]
  44
  45
  46 # Fast SPRs Regfile
  47 class FastRegs(RegFileArray):
  48     """FastRegs
  49
  50     FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  51
  52     * QTY 8of 64-bit registers
  53     * 3R2W
  54     * Array-based unary-indexed (not binary-indexed)
  55     * write-through capability (read on same cycle as write)
  56     """
  57     PC = 0
  58     MSR = 1
  59     CTR = 2
  60     LR = 3
  61     TAR = 4
  62     SRR1 = 5
  63     SRR2 = 6
  64     def __init__(self):
  65         super().__init__(64, 8)
  66         self.w_ports = [self.write_port("dest1"),
  67                         self.write_port("dest2")]
  68         self.r_ports = [self.read_port("src1"),
  69                         self.read_port("src2"),
  70                         self.read_port("src3")]
  71
  72
  73 # CR Regfile
  74 class CRRegs(VirtualRegPort):
  75     """Condition Code Registers (CR0-7)
  76
  77     * QTY 8of 8-bit registers
  78     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
  79     * Array-based unary-indexed (not binary-indexed)
  80     * write-through capability (read on same cycle as write)
  81     """
  82     def __init__(self):
  83         super().__init__(32, 8)
  84         self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
  85                         self.write_port("dest")] # 4-bit wide, unary-indexed
  86         self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
  87                         self.read_port("src1"),
  88                         self.read_port("src2"),
  89                         self.read_port("src3")]
  90
  91
  92 # XER Regfile
  93 class XERRegs(VirtualRegPort):
  94     """XER Registers (SO, CA/CA32, OV/OV32)
  95
  96     * QTY 3of 2-bit registers
  97     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
  98     * Array-based unary-indexed (not binary-indexed)
  99     * write-through capability (read on same cycle as write)
 100     """
 101     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 102     CA=1 # CA and CA32
 103     OV=2 # OV and OV32
 104     def __init__(self):
 105         super().__init__(6, 2)
 106         self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
 107                         self.write_port("dest1"),
 108                         self.write_port("dest2"),
 109                         self.write_port("dest3")]
 110         self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
 111                         self.read_port("src1"),
 112                         self.read_port("src2"),
 113                         self.read_port("src3")]
 114
 115
 116 # SPR Regfile
 117 class SPRRegs(RegFile):
 118     """SPRRegs
 119
 120     * QTY len(SPRs) 64-bit registers
 121     * 1R1W
 122     * binary-indexed but REQUIRES MAPPING
 123     * write-through capability (read on same cycle as write)
 124     """
 125     def __init__(self):
 126         n_sprs = len(SPR)
 127         super().__init__(64, n_sprs)
 128         self.w_ports = [self.write_port("dest")]
 129         self.r_ports = [self.read_port("src")]
 130
 131 # class containing all regfiles: int, cr, xer, fast, spr
 132 class RegFiles(Elaboratable):
 133     def __init__(self):
 134         self.rf = {}
 135         for (name, kls) in [('int', IntRegs),
 136                             ('cr', CRRegs),
 137                             ('xer', XERRegs),
 138                             ('fasr', FastRegs),
 139                             ('spr', SPRRegs),]:
 140             rf = self.rf[name] = kls()
 141             setattr(self, name, rf)
 142
 143     def elaborate(self, platform):
 144         m = Module()
 145         for (name, rf) in self.rf.items():
 146             setattr(m.submodules, name, rf)
 147         return m
 148