1 # POWER9 Register Files
4 Defines the following register files:
6 * INT regfile - 32x 64-bit
7 * SPR regfile - 110x 64-bit
9 * XER regfile - XER.so, XER.ca/ca32, XER.ov/ov32
10 * FAST regfile - CTR, LR, TAR, SRR1, SRR2
11 * STATE regfile - PC, MSR, (SimpleV VL later)
13 Note: this should NOT have name conventions hard-coded (dedicated ports per
14 regname). However it is convenient for now.
18 * https://bugs.libre-soc.org/show_bug.cgi?id=345
19 * https://bugs.libre-soc.org/show_bug.cgi?id=351
20 * https://libre-soc.org/3d_gpu/architecture/regfile/
21 * https://libre-soc.org/openpower/isatables/sprs.csv
26 from soc
.regfile
.regfile
import RegFile
, RegFileArray
, RegFileMem
27 from soc
.regfile
.virtual_port
import VirtualRegPort
28 from soc
.decoder
.power_enums
import SPR
32 class StateRegs(RegFileArray
):
35 State regfile - PC, MSR and later SimpleV VL
37 * QTY 2of 64-bit registers
39 * Array-based unary-indexed (not binary-indexed)
40 * write-through capability (read on same cycle as write)
42 Note: d_wr1 d_rd1 are for use by the decoder, to get at the PC.
43 will probably have to also add one so it can get at the MSR as well.
49 super().__init
__(64, 2)
50 self
.w_ports
= {'nia': self
.write_port("nia"),
51 'msr': self
.write_port("msr"),
52 'd_wr1': self
.write_port("d_wr1")} # writing PC (issuer)
53 self
.r_ports
= {'cia': self
.read_port("cia"), # reading PC (issuer)
54 'msr': self
.read_port("msr"), # reading MSR (issuer)
59 class IntRegs(RegFileArray
):
62 * QTY 32of 64-bit registers
64 * Array-based unary-indexed (not binary-indexed)
65 * write-through capability (read on same cycle as write)
68 super().__init
__(64, 32)
69 self
.w_ports
= {'o': self
.write_port("dest1"),
70 #'o1': self.write_port("dest2") # for now (LD/ST update)
72 self
.r_ports
= {'rabc': self
.read_port("src1"),
73 #'rbc': self.read_port("src3"),
74 'dmi': self
.read_port("dmi")} # needed for Debug (DMI)
78 class FastRegs(RegFileArray
):
81 FAST regfile - CTR, LR, TAR, SRR1, SRR2
83 * QTY 5of 64-bit registers
85 * Array-based unary-indexed (not binary-indexed)
86 * write-through capability (read on same cycle as write)
94 super().__init
__(64, 5)
95 self
.w_ports
= {'fast1': self
.write_port("dest3"),
97 self
.r_ports
= {'fast1': self
.read_port("src1"),
102 class CRRegs(VirtualRegPort
):
103 """Condition Code Registers (CR0-7)
105 * QTY 8of 8-bit registers
106 * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
107 * Array-based unary-indexed (not binary-indexed)
108 * write-through capability (read on same cycle as write)
111 super().__init
__(32, 8)
112 self
.w_ports
= {'full_cr': self
.full_wr
, # 32-bit (masked, 8-en lines)
113 'cr_a': self
.write_port("dest1"), # 4-bit, unary-indexed
114 'cr_b': self
.write_port("dest2")} # 4-bit, unary-indexed
115 self
.r_ports
= {'full_cr': self
.full_rd
, # 32-bit (masked, 8-en lines)
116 'cr_a': self
.read_port("src1"),
117 'cr_b': self
.read_port("src2"),
118 'cr_c': self
.read_port("src3")}
122 class XERRegs(VirtualRegPort
):
123 """XER Registers (SO, CA/CA32, OV/OV32)
125 * QTY 3of 2-bit registers
126 * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
127 * Array-based unary-indexed (not binary-indexed)
128 * write-through capability (read on same cycle as write)
130 SO
=0 # this is actually 2-bit but we ignore 1 bit of it
134 super().__init
__(6, 3)
135 self
.w_ports
= {'full_xer': self
.full_wr
, # 6-bit (masked, 3-en lines)
136 'xer_so': self
.write_port("dest1"),
137 'xer_ca': self
.write_port("dest2"),
138 'xer_ov': self
.write_port("dest3")}
139 self
.r_ports
= {'full_xer': self
.full_rd
, # 6-bit (masked, 3-en lines)
140 'xer_so': self
.read_port("src1"),
141 'xer_ca': self
.read_port("src2"),
142 'xer_ov': self
.read_port("src3")}
146 class SPRRegs(RegFileMem
):
149 * QTY len(SPRs) 64-bit registers
151 * binary-indexed but REQUIRES MAPPING
152 * write-through capability (read on same cycle as write)
156 super().__init
__(width
=64, depth
=n_sprs
)
157 self
.w_ports
= {'spr1': self
.write_port("spr1")}
158 self
.r_ports
= {'spr1': self
.read_port("spr1")}
160 # make read/write ports look like RegFileArray
161 self
.w_ports
['spr1'].wen
= self
.w_ports
['spr1'].en
162 self
.w_ports
['spr1'].data_i
= self
.w_ports
['spr1'].data
164 self
.r_ports
['spr1'].ren
= self
.w_ports
['spr1'].en
165 self
.r_ports
['spr1'].data_o
= self
.w_ports
['spr1'].data
168 # class containing all regfiles: int, cr, xer, fast, spr
172 for (name
, kls
) in [('int', IntRegs
),
176 ('state', StateRegs
),
178 rf
= self
.rf
[name
] = kls()
179 setattr(self
, name
, rf
)
181 def elaborate_into(self
, m
, platform
):
182 for (name
, rf
) in self
.rf
.items():
183 setattr(m
.submodules
, name
, rf
)