1 from nmigen
import Signal
, Module
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
5 from soc
.alu
.maskgen
import MaskGen
6 from soc
.decoder
.helpers
import MASK
10 class MaskGenTestCase(FHDLTestCase
):
11 def test_maskgen(self
):
14 m
.submodules
.dut
= dut
= MaskGen(64)
15 mb
= Signal
.like(dut
.mb
)
16 me
= Signal
.like(dut
.me
)
17 o
= Signal
.like(dut
.o
)
27 for x
in range(0, 64):
28 for y
in range(0, 64):
35 self
.assertEqual(expected
, result
)
37 sim
.add_process(process
) # or sim.add_sync_process(process), see below
38 with sim
.write_vcd("maskgen.vcd", "maskgen.gtkw", traces
=dut
.ports()):
43 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
44 with
open("maskgen.il", "w") as f
:
47 if __name__
== '__main__':