src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.decoder.decode2execute1 import Data
  33 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  34 from soc.config.test.test_loadstore import TestMemPspec
  35 from soc.decoder.power_enums import MicrOp
  36 import operator
  37
  38
  39 # helper function for reducing a list of signals down to a parallel
  40 # ORed single signal.
  41 def ortreereduce(tree, attr="data_o"):
  42     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  43
  44
  45 def ortreereduce_sig(tree):
  46     return treereduce(tree, operator.or_, lambda x: x)
  47
  48
  49 # helper function to place full regs declarations first
  50 def sort_fuspecs(fuspecs):
  51     res = []
  52     for (regname, fspec) in fuspecs.items():
  53         if regname.startswith("full"):
  54             res.append((regname, fspec))
  55     for (regname, fspec) in fuspecs.items():
  56         if not regname.startswith("full"):
  57             res.append((regname, fspec))
  58     return res  # enumerate(res)
  59
  60
  61 class NonProductionCore(Elaboratable):
  62     def __init__(self, pspec):
  63         # single LD/ST funnel for memory access
  64         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
  65         pi = self.l0.l0.dports[0]
  66
  67         # function units (only one each)
  68         self.fus = AllFunctionUnits(pspec, pilist=[pi])
  69
  70         # register files (yes plural)
  71         self.regs = RegFiles()
  72
  73         # instruction decoder
  74         pdecode = create_pdecode()
  75         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  76
  77         # issue/valid/busy signalling
  78         self.ivalid_i = self.pdecode2.valid   # instruction is valid
  79         self.issue_i = Signal(reset_less=True)
  80         self.busy_o = Signal(name="corebusy_o", reset_less=True)
  81
  82         # instruction input
  83         self.bigendian_i = self.pdecode2.dec.bigendian
  84         self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
  85
  86         # start/stop and terminated signalling
  87         self.core_start_i = Signal(reset_less=True)
  88         self.core_stop_i = Signal(reset_less=True)
  89         self.core_terminated_o = Signal(reset=0)  # indicates stopped
  90
  91     def elaborate(self, platform):
  92         m = Module()
  93
  94         m.submodules.pdecode2 = dec2 = self.pdecode2
  95         m.submodules.fus = self.fus
  96         m.submodules.l0 = l0 = self.l0
  97         self.regs.elaborate_into(m, platform)
  98         regs = self.regs
  99         fus = self.fus.fus
 100
 101         # core start/stopped state
 102         core_stopped = Signal(reset=1)  # begins in stopped state
 103
 104         # start/stop signalling
 105         with m.If(self.core_start_i):
 106             m.d.sync += core_stopped.eq(0)
 107         with m.If(self.core_stop_i):
 108             m.d.sync += core_stopped.eq(1)
 109         m.d.comb += self.core_terminated_o.eq(core_stopped)
 110
 111         # connect up Function Units, then read/write ports
 112         fu_bitdict = self.connect_instruction(m, core_stopped)
 113         self.connect_rdports(m, fu_bitdict)
 114         self.connect_wrports(m, fu_bitdict)
 115
 116         return m
 117
 118     def connect_instruction(self, m, core_stopped):
 119         """connect_instruction
 120
 121         uses decoded (from PowerOp) function unit information from CSV files
 122         to ascertain which Function Unit should deal with the current
 123         instruction.
 124
 125         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 126         ignoring it and halting the processor.  OP_NOP is a bit annoying
 127         because the issuer expects busy flag still to be raised then lowered.
 128         (this requires a fake counter to be set).
 129         """
 130         comb, sync = m.d.comb, m.d.sync
 131         fus = self.fus.fus
 132         dec2 = self.pdecode2
 133
 134         # enable-signals for each FU, get one bit for each FU (by name)
 135         fu_enable = Signal(len(fus), reset_less=True)
 136         fu_bitdict = {}
 137         for i, funame in enumerate(fus.keys()):
 138             fu_bitdict[funame] = fu_enable[i]
 139         # only run when allowed and when instruction is valid
 140         can_run = Signal(reset_less=True)
 141         comb += can_run.eq(self.ivalid_i & ~core_stopped)
 142
 143         # enable the required Function Unit based on the opcode decode
 144         # note: this *only* works correctly for simple core when one and
 145         # *only* one FU is allocated per instruction
 146         for funame, fu in fus.items():
 147             fnunit = fu.fnunit.value
 148             enable = Signal(name="en_%s" % funame, reset_less=True)
 149             comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool())
 150             comb += fu_bitdict[funame].eq(enable)
 151
 152         # sigh - need a NOP counter
 153         counter = Signal(2)
 154         with m.If(counter != 0):
 155             sync += counter.eq(counter - 1)
 156             comb += self.busy_o.eq(1)
 157
 158         with m.If(can_run):
 159             with m.Switch(dec2.e.do.insn_type):
 160                 # check for ATTN: halt if true
 161                 with m.Case(MicrOp.OP_ATTN):
 162                     m.d.sync += core_stopped.eq(1)
 163
 164                 with m.Case(MicrOp.OP_NOP):
 165                     sync += counter.eq(2)
 166                     comb += self.busy_o.eq(1)
 167
 168                 with m.Default():
 169                     # connect up instructions.  only one enabled at a time
 170                     for funame, fu in fus.items():
 171                         enable = fu_bitdict[funame]
 172
 173                         # run this FunctionUnit if enabled
 174                         with m.If(enable):
 175                             # route op, issue, busy, read flags and mask to FU
 176                             comb += fu.oper_i.eq_from_execute1(dec2.e)
 177                             comb += fu.issue_i.eq(self.issue_i)
 178                             comb += self.busy_o.eq(fu.busy_o)
 179                             rdmask = dec2.rdflags(fu)
 180                             comb += fu.rdmaskn.eq(~rdmask)
 181
 182         return fu_bitdict
 183
 184     def connect_rdports(self, m, fu_bitdict):
 185         """connect read ports
 186
 187         orders the read regspecs into a dict-of-dicts, by regfile, by
 188         regport name, then connects all FUs that want that regport by
 189         way of a PriorityPicker.
 190         """
 191         comb, sync = m.d.comb, m.d.sync
 192         fus = self.fus.fus
 193         regs = self.regs
 194
 195         # dictionary of lists of regfile read ports
 196         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 197
 198         # okaay, now we need a PriorityPicker per regfile per regfile port
 199         # loootta pickers... peter piper picked a pack of pickled peppers...
 200         rdpickers = {}
 201         for regfile, spec in byregfiles_rd.items():
 202             fuspecs = byregfiles_rdspec[regfile]
 203             rdpickers[regfile] = {}
 204
 205             # for each named regfile port, connect up all FUs to that port
 206             for (regname, fspec) in sort_fuspecs(fuspecs):
 207                 print("connect rd", regname, fspec)
 208                 rpidx = regname
 209                 # get the regfile specs for this regfile port
 210                 (rf, read, write, wid, fuspec) = fspec
 211                 name = "rdflag_%s_%s" % (regfile, regname)
 212                 rdflag = Signal(name=name, reset_less=True)
 213                 comb += rdflag.eq(rf)
 214
 215                 # select the required read port.  these are pre-defined sizes
 216                 print(rpidx, regfile, regs.rf.keys())
 217                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 218
 219                 # create a priority picker to manage this port
 220                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(
 221                     len(fuspec))
 222                 setattr(m.submodules, "rdpick_%s_%s" %
 223                         (regfile, rpidx), rdpick)
 224
 225                 # connect the regspec "reg select" number to this port
 226                 with m.If(rdpick.en_o):
 227                     comb += rport.ren.eq(read)
 228
 229                 # connect up the FU req/go signals, and the reg-read to the FU
 230                 # and create a Read Broadcast Bus
 231                 for pi, (funame, fu, idx) in enumerate(fuspec):
 232                     src = fu.src_i[idx]
 233
 234                     # connect request-read to picker input, and output to go-rd
 235                     fu_active = fu_bitdict[funame]
 236                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 237                     comb += rdpick.i[pi].eq(pick)
 238                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 239
 240                     # connect regfile port to input, creating a Broadcast Bus
 241                     print("reg connect widths",
 242                           regfile, regname, pi, funame,
 243                           src.shape(), rport.data_o.shape())
 244                     # all FUs connect to same port
 245                     comb += src.eq(rport.data_o)
 246
 247     def connect_wrports(self, m, fu_bitdict):
 248         """connect write ports
 249
 250         orders the write regspecs into a dict-of-dicts, by regfile,
 251         by regport name, then connects all FUs that want that regport
 252         by way of a PriorityPicker.
 253
 254         note that the write-port wen, write-port data, and go_wr_i all need to
 255         be on the exact same clock cycle.  as there is a combinatorial loop bug
 256         at the moment, these all use sync.
 257         """
 258         comb, sync = m.d.comb, m.d.sync
 259         fus = self.fus.fus
 260         regs = self.regs
 261         # dictionary of lists of regfile write ports
 262         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 263
 264         # same for write ports.
 265         # BLECH!  complex code-duplication! BLECH!
 266         wrpickers = {}
 267         for regfile, spec in byregfiles_wr.items():
 268             fuspecs = byregfiles_wrspec[regfile]
 269             wrpickers[regfile] = {}
 270             for (regname, fspec) in sort_fuspecs(fuspecs):
 271                 print("connect wr", regname, fspec)
 272                 rpidx = regname
 273                 # get the regfile specs for this regfile port
 274                 (rf, read, write, wid, fuspec) = fspec
 275
 276                 # select the required write port.  these are pre-defined sizes
 277                 print(regfile, regs.rf.keys())
 278                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 279
 280                 # create a priority picker to manage this port
 281                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(
 282                     len(fuspec))
 283                 setattr(m.submodules, "wrpick_%s_%s" %
 284                         (regfile, rpidx), wrpick)
 285
 286                 # connect the regspec write "reg select" number to this port
 287                 # only if one FU actually requests (and is granted) the port
 288                 # will the write-enable be activated
 289                 with m.If(wrpick.en_o):
 290                     comb += wport.wen.eq(write)
 291                 with m.Else():
 292                     comb += wport.wen.eq(0)
 293
 294                 # connect up the FU req/go signals and the reg-read to the FU
 295                 # these are arbitrated by Data.ok signals
 296                 wsigs = []
 297                 for pi, (funame, fu, idx) in enumerate(fuspec):
 298                     # write-request comes from dest.ok
 299                     dest = fu.get_out(idx)
 300                     fu_dest_latch = fu.get_fu_out(idx)  # latched output
 301                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 302                     wrflag = Signal(name=name, reset_less=True)
 303                     comb += wrflag.eq(dest.ok & fu.busy_o)
 304
 305                     # connect request-read to picker input, and output to go-wr
 306                     fu_active = fu_bitdict[funame]
 307                     pick = fu.wr.rel[idx] & fu_active  # & wrflag
 308                     comb += wrpick.i[pi].eq(pick)
 309                     comb += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 310                     # connect regfile port to input
 311                     print("reg connect widths",
 312                           regfile, regname, pi, funame,
 313                           dest.shape(), wport.data_i.shape())
 314                     wsigs.append(fu_dest_latch)
 315
 316                 # here is where we create the Write Broadcast Bus. simple, eh?
 317                 comb += wport.data_i.eq(ortreereduce_sig(wsigs))
 318
 319     def get_byregfiles(self, readmode):
 320
 321         mode = "read" if readmode else "write"
 322         dec2 = self.pdecode2
 323         regs = self.regs
 324         fus = self.fus.fus
 325
 326         # dictionary of lists of regfile ports
 327         byregfiles = {}
 328         byregfiles_spec = {}
 329         for (funame, fu) in fus.items():
 330             print("%s ports for %s" % (mode, funame))
 331             for idx in range(fu.n_src if readmode else fu.n_dst):
 332                 if readmode:
 333                     (regfile, regname, wid) = fu.get_in_spec(idx)
 334                 else:
 335                     (regfile, regname, wid) = fu.get_out_spec(idx)
 336                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 337                 if readmode:
 338                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 339                     write = None
 340                 else:
 341                     rdflag, read = None, None
 342                     wrport, write = dec2.regspecmap_write(regfile, regname)
 343                 if regfile not in byregfiles:
 344                     byregfiles[regfile] = {}
 345                     byregfiles_spec[regfile] = {}
 346                 if regname not in byregfiles_spec[regfile]:
 347                     byregfiles_spec[regfile][regname] = \
 348                         [rdflag, read, write, wid, []]
 349                 # here we start to create "lanes"
 350                 if idx not in byregfiles[regfile]:
 351                     byregfiles[regfile][idx] = []
 352                 fuspec = (funame, fu, idx)
 353                 byregfiles[regfile][idx].append(fuspec)
 354                 byregfiles_spec[regfile][regname][4].append(fuspec)
 355
 356         # ok just print that out, for convenience
 357         for regfile, spec in byregfiles.items():
 358             print("regfile %s ports:" % mode, regfile)
 359             fuspecs = byregfiles_spec[regfile]
 360             for regname, fspec in fuspecs.items():
 361                 [rdflag, read, write, wid, fuspec] = fspec
 362                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 363                 print("  %s" % regname, wid, read, write, rdflag)
 364                 for (funame, fu, idx) in fuspec:
 365                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 366                     print("    ", funame, fu, idx, fusig)
 367                     print()
 368
 369         return byregfiles, byregfiles_spec
 370
 371     def __iter__(self):
 372         yield from self.fus.ports()
 373         yield from self.pdecode2.ports()
 374         yield from self.l0.ports()
 375         # TODO: regs
 376
 377     def ports(self):
 378         return list(self)
 379
 380
 381 if __name__ == '__main__':
 382     pspec = TestMemPspec(ldst_ifacetype='testpi',
 383                          imem_ifacetype='',
 384                          addr_wid=48,
 385                          mask_wid=8,
 386                          reg_wid=64)
 387     dut = NonProductionCore(pspec)
 388     vl = rtlil.convert(dut, ports=dut.ports())
 389     with open("test_core.il", "w") as f:
 390         f.write(vl)