3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
23 from nmigen
.cli
import rtlil
25 from nmutil
.picker
import PriorityPicker
26 from nmutil
.util
import treereduce
28 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
29 from soc
.regfile
.regfiles
import RegFiles
30 from soc
.decoder
.power_decoder
import create_pdecode
31 from soc
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.decoder
.decode2execute1
import Data
33 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
34 from soc
.config
.test
.test_loadstore
import TestMemPspec
35 from soc
.decoder
.power_enums
import InternalOp
39 # helper function for reducing a list of signals down to a parallel
41 def ortreereduce(tree
, attr
="data_o"):
42 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
45 # helper function to place full regs declarations first
46 def sort_fuspecs(fuspecs
):
48 for (regname
, fspec
) in fuspecs
.items():
49 if regname
.startswith("full"):
50 res
.append((regname
, fspec
))
51 for (regname
, fspec
) in fuspecs
.items():
52 if not regname
.startswith("full"):
53 res
.append((regname
, fspec
))
54 return res
# enumerate(res)
57 class NonProductionCore(Elaboratable
):
58 def __init__(self
, pspec
):
59 # single LD/ST funnel for memory access
60 self
.l0
= TstL0CacheBuffer(pspec
, n_units
=1)
61 pi
= self
.l0
.l0
.dports
[0]
63 # function units (only one each)
64 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
66 # register files (yes plural)
67 self
.regs
= RegFiles()
70 pdecode
= create_pdecode()
71 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
73 # issue/valid/busy signalling
74 self
.ivalid_i
= self
.pdecode2
.valid
# instruction is valid
75 self
.issue_i
= Signal(reset_less
=True)
76 self
.busy_o
= Signal(name
="corebusy_o", reset_less
=True)
79 self
.bigendian_i
= self
.pdecode2
.dec
.bigendian
80 self
.raw_opcode_i
= self
.pdecode2
.dec
.raw_opcode_in
82 # start/stop and terminated signalling
83 self
.core_start_i
= Signal(reset_less
=True)
84 self
.core_stop_i
= Signal(reset_less
=True)
85 self
.core_terminated_o
= Signal(reset
=1) # indicates stopped
87 def elaborate(self
, platform
):
90 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
91 m
.submodules
.fus
= self
.fus
92 m
.submodules
.l0
= l0
= self
.l0
93 self
.regs
.elaborate_into(m
, platform
)
97 # core start/stopped state
98 core_stopped
= Signal(reset
=1) # begins in stopped state
100 # start/stop signalling
101 with m
.If(self
.core_start_i
):
102 m
.d
.sync
+= core_stopped
.eq(0)
103 with m
.If(self
.core_stop_i
):
104 m
.d
.sync
+= core_stopped
.eq(1)
105 m
.d
.comb
+= self
.core_terminated_o
.eq(core_stopped
)
107 # connect up Function Units, then read/write ports
108 fu_bitdict
= self
.connect_instruction(m
, core_stopped
)
109 self
.connect_rdports(m
, fu_bitdict
)
110 self
.connect_wrports(m
, fu_bitdict
)
114 def connect_instruction(self
, m
, core_stopped
):
115 comb
, sync
= m
.d
.comb
, m
.d
.sync
119 # enable-signals for each FU, get one bit for each FU (by name)
120 fu_enable
= Signal(len(fus
), reset_less
=True)
122 for i
, funame
in enumerate(fus
.keys()):
123 fu_bitdict
[funame
] = fu_enable
[i
]
124 # only run when allowed and when instruction is valid
125 can_run
= Signal(reset_less
=True)
126 comb
+= can_run
.eq(self
.ivalid_i
& ~core_stopped
)
128 # enable the required Function Unit based on the opcode decode
129 # note: this *only* works correctly for simple core when one and
130 # *only* one FU is allocated per instruction
131 for funame
, fu
in fus
.items():
132 fnunit
= fu
.fnunit
.value
133 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
134 comb
+= enable
.eq((dec2
.e
.do
.fn_unit
& fnunit
).bool() & can_run
)
135 comb
+= fu_bitdict
[funame
].eq(enable
)
137 # sigh - need a NOP counter
139 with m
.If(counter
!= 0):
140 sync
+= counter
.eq(counter
- 1)
141 comb
+= self
.busy_o
.eq(counter
!= 0)
143 # check for ATTN: halt if true
144 with m
.If(self
.ivalid_i
& (dec2
.e
.do
.insn_type
== InternalOp
.OP_ATTN
)):
145 m
.d
.sync
+= core_stopped
.eq(1)
147 with m
.Elif(can_run
& (dec2
.e
.do
.insn_type
== InternalOp
.OP_NOP
)):
148 sync
+= counter
.eq(2)
149 comb
+= self
.busy_o
.eq(1)
152 # connect up instructions. only one is enabled at any given time
153 for funame
, fu
in fus
.items():
154 enable
= fu_bitdict
[funame
]
156 # run this FunctionUnit if enabled, except if the instruction
157 # is "attn" in which case we HALT.
159 # route operand, issue, busy, read flags and mask to FU
160 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
161 comb
+= fu
.issue_i
.eq(self
.issue_i
)
162 comb
+= self
.busy_o
.eq(fu
.busy_o
)
163 rdmask
= dec2
.rdflags(fu
)
164 comb
+= fu
.rdmaskn
.eq(~rdmask
)
168 def connect_rdports(self
, m
, fu_bitdict
):
169 """connect read ports
171 orders the read regspecs into a dict-of-dicts, by regfile, by
172 regport name, then connects all FUs that want that regport by
173 way of a PriorityPicker.
175 comb
, sync
= m
.d
.comb
, m
.d
.sync
179 # dictionary of lists of regfile read ports
180 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
182 # okaay, now we need a PriorityPicker per regfile per regfile port
183 # loootta pickers... peter piper picked a pack of pickled peppers...
185 for regfile
, spec
in byregfiles_rd
.items():
186 fuspecs
= byregfiles_rdspec
[regfile
]
187 rdpickers
[regfile
] = {}
189 # for each named regfile port, connect up all FUs to that port
190 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
191 print ("connect rd", regname
, fspec
)
193 # get the regfile specs for this regfile port
194 (rf
, read
, write
, wid
, fuspec
) = fspec
195 name
= "rdflag_%s_%s" % (regfile
, regname
)
196 rdflag
= Signal(name
=name
, reset_less
=True)
197 comb
+= rdflag
.eq(rf
)
199 # select the required read port. these are pre-defined sizes
200 print (rpidx
, regfile
, regs
.rf
.keys())
201 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
203 # create a priority picker to manage this port
204 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(len(fuspec
))
205 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
207 # connect the regspec "reg select" number to this port
208 with m
.If(rdpick
.en_o
):
209 comb
+= rport
.ren
.eq(read
)
211 # connect up the FU req/go signals, and the reg-read to the FU
212 # and create a Read Broadcast Bus
213 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
216 # connect request-read to picker input, and output to go-rd
217 fu_active
= fu_bitdict
[funame
]
218 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
219 comb
+= rdpick
.i
[pi
].eq(pick
)
220 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
222 # connect regfile port to input, creating a Broadcast Bus
223 print ("reg connect widths",
224 regfile
, regname
, pi
, funame
,
225 src
.shape(), rport
.data_o
.shape())
226 comb
+= src
.eq(rport
.data_o
) # all FUs connect to same port
228 def connect_wrports(self
, m
, fu_bitdict
):
229 """connect write ports
231 orders the write regspecs into a dict-of-dicts, by regfile,
232 by regport name, then connects all FUs that want that regport
233 by way of a PriorityPicker.
235 note that the write-port wen, write-port data, and go_wr_i all need to
236 be on the exact same clock cycle. as there is a combinatorial loop bug
237 at the moment, these all use sync.
239 comb
, sync
= m
.d
.comb
, m
.d
.sync
242 # dictionary of lists of regfile write ports
243 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
245 # same for write ports.
246 # BLECH! complex code-duplication! BLECH!
248 for regfile
, spec
in byregfiles_wr
.items():
249 fuspecs
= byregfiles_wrspec
[regfile
]
250 wrpickers
[regfile
] = {}
251 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
252 print ("connect wr", regname
, fspec
)
254 # get the regfile specs for this regfile port
255 (rf
, read
, write
, wid
, fuspec
) = fspec
257 # select the required write port. these are pre-defined sizes
258 print (regfile
, regs
.rf
.keys())
259 wport
= regs
.rf
[regfile
.lower()].w_ports
[rpidx
]
261 # create a priority picker to manage this port
262 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(len(fuspec
))
263 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
265 # connect the regspec write "reg select" number to this port
266 # only if one FU actually requests (and is granted) the port
267 # will the write-enable be activated
268 with m
.If(wrpick
.en_o
):
269 sync
+= wport
.wen
.eq(write
)
271 sync
+= wport
.wen
.eq(0)
273 # connect up the FU req/go signals and the reg-read to the FU
274 # these are arbitrated by Data.ok signals
276 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
277 # write-request comes from dest.ok
278 dest
= fu
.get_out(idx
)
279 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
280 wrflag
= Signal(name
=name
, reset_less
=True)
281 comb
+= wrflag
.eq(dest
.ok
& fu
.busy_o
)
283 # connect request-read to picker input, and output to go-wr
284 fu_active
= fu_bitdict
[funame
]
285 pick
= fu
.wr
.rel
[idx
] & fu_active
#& wrflag
286 comb
+= wrpick
.i
[pi
].eq(pick
)
287 sync
+= fu
.go_wr_i
[idx
].eq(wrpick
.o
[pi
] & wrpick
.en_o
)
288 # connect regfile port to input
289 print ("reg connect widths",
290 regfile
, regname
, pi
, funame
,
291 dest
.shape(), wport
.data_i
.shape())
294 # here is where we create the Write Broadcast Bus. simple, eh?
295 sync
+= wport
.data_i
.eq(ortreereduce(wsigs
, "data"))
297 def get_byregfiles(self
, readmode
):
299 mode
= "read" if readmode
else "write"
304 # dictionary of lists of regfile ports
307 for (funame
, fu
) in fus
.items():
308 print ("%s ports for %s" % (mode
, funame
))
309 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
311 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
313 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
314 print (" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
316 rdflag
, read
= dec2
.regspecmap_read(regfile
, regname
)
319 rdflag
, read
= None, None
320 wrport
, write
= dec2
.regspecmap_write(regfile
, regname
)
321 if regfile
not in byregfiles
:
322 byregfiles
[regfile
] = {}
323 byregfiles_spec
[regfile
] = {}
324 if regname
not in byregfiles_spec
[regfile
]:
325 byregfiles_spec
[regfile
][regname
] = \
326 [rdflag
, read
, write
, wid
, []]
327 # here we start to create "lanes"
328 if idx
not in byregfiles
[regfile
]:
329 byregfiles
[regfile
][idx
] = []
330 fuspec
= (funame
, fu
, idx
)
331 byregfiles
[regfile
][idx
].append(fuspec
)
332 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
334 # ok just print that out, for convenience
335 for regfile
, spec
in byregfiles
.items():
336 print ("regfile %s ports:" % mode
, regfile
)
337 fuspecs
= byregfiles_spec
[regfile
]
338 for regname
, fspec
in fuspecs
.items():
339 [rdflag
, read
, write
, wid
, fuspec
] = fspec
340 print (" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
341 print (" %s" % regname
, wid
, read
, write
, rdflag
)
342 for (funame
, fu
, idx
) in fuspec
:
343 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
344 print (" ", funame
, fu
, idx
, fusig
)
347 return byregfiles
, byregfiles_spec
350 yield from self
.fus
.ports()
351 yield from self
.pdecode2
.ports()
352 yield from self
.l0
.ports()
359 if __name__
== '__main__':
360 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
365 dut
= NonProductionCore(pspec
)
366 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
367 with
open("test_core.il", "w") as f
: