src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
  33 import operator
  34
  35
  36 # helper function for reducing a list of signals down to a parallel
  37 # ORed single signal.
  38 def ortreereduce(tree, attr="data_o"):
  39     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  40
  41 # helper function to place full regs declarations first
  42 def sort_fuspecs(fuspecs):
  43     res = []
  44     for (regname, fspec) in fuspecs.items():
  45         if regname.startswith("full"):
  46             res.append((regname, fspec))
  47     for (regname, fspec) in fuspecs.items():
  48         if not regname.startswith("full"):
  49             res.append((regname, fspec))
  50     return res # enumerate(res)
  51
  52
  53 class NonProductionCore(Elaboratable):
  54     def __init__(self, addrwid=6):
  55         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
  56         pi = self.l0.l0.dports[0].pi
  57
  58         self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)
  59         self.regs = RegFiles()
  60         self.pdecode = pdecode = create_pdecode()
  61         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  62         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  63         self.issue_i = Signal(reset_less=True)
  64         self.busy_o = Signal(reset_less=True)
  65
  66     def elaborate(self, platform):
  67         m = Module()
  68
  69         m.submodules.pdecode2 = dec2 = self.pdecode2
  70         m.submodules.fus = self.fus
  71         m.submodules.l0 = l0 = self.l0
  72         self.regs.elaborate_into(m, platform)
  73         regs = self.regs
  74         fus = self.fus.fus
  75
  76         fu_bitdict = self.connect_instruction(m)
  77         self.connect_rdports(m, fu_bitdict)
  78         self.connect_wrports(m, fu_bitdict)
  79
  80         return m
  81
  82     def connect_instruction(self, m):
  83         comb, sync = m.d.comb, m.d.sync
  84         fus = self.fus.fus
  85         dec2 = self.pdecode2
  86
  87         # enable-signals for each FU, get one bit for each FU (by name)
  88         fu_enable = Signal(len(fus), reset_less=True)
  89         fu_bitdict = {}
  90         for i, funame in enumerate(fus.keys()):
  91             fu_bitdict[funame] = fu_enable[i]
  92
  93         # connect up instructions.  only one is enabled at any given time
  94         for funame, fu in fus.items():
  95             fnunit = fu.fnunit.value
  96             enable = Signal(name="en_%s" % funame, reset_less=True)
  97             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
  98             with m.If(enable):
  99                 comb += fu.oper_i.eq_from_execute1(dec2.e)
 100                 comb += fu.issue_i.eq(self.issue_i)
 101                 comb += self.busy_o.eq(fu.busy_o)
 102                 rdmask = dec2.rdflags(fu)
 103                 comb += fu.rdmaskn.eq(~rdmask)
 104             comb += fu_bitdict[funame].eq(enable)
 105
 106         return fu_bitdict
 107
 108     def connect_rdports(self, m, fu_bitdict):
 109         """connect read ports
 110
 111         orders the read regspecs into a dict-of-dicts, by regfile, by
 112         regport name, then connects all FUs that want that regport by
 113         way of a PriorityPicker.
 114         """
 115         comb, sync = m.d.comb, m.d.sync
 116         fus = self.fus.fus
 117         regs = self.regs
 118
 119         # dictionary of lists of regfile read ports
 120         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 121
 122         # okaay, now we need a PriorityPicker per regfile per regfile port
 123         # loootta pickers... peter piper picked a pack of pickled peppers...
 124         rdpickers = {}
 125         for regfile, spec in byregfiles_rd.items():
 126             fuspecs = byregfiles_rdspec[regfile]
 127             rdpickers[regfile] = {}
 128
 129             # for each named regfile port, connect up all FUs to that port
 130             for (regname, fspec) in sort_fuspecs(fuspecs):
 131                 print ("connect rd", regname, fspec)
 132                 rpidx = regname
 133                 # get the regfile specs for this regfile port
 134                 (rf, read, write, wid, fuspec) = fspec
 135                 name = "rdflag_%s_%s" % (regfile, regname)
 136                 rdflag = Signal(name=name, reset_less=True)
 137                 comb += rdflag.eq(rf)
 138
 139                 # select the required read port.  these are pre-defined sizes
 140                 print (rpidx, regfile, regs.rf.keys())
 141                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 142
 143                 # create a priority picker to manage this port
 144                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 145                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 146
 147                 # connect the regspec "reg select" number to this port
 148                 with m.If(rdpick.en_o):
 149                     comb += rport.ren.eq(read)
 150
 151                 # connect up the FU req/go signals, and the reg-read to the FU
 152                 # and create a Read Broadcast Bus
 153                 for pi, (funame, fu, idx) in enumerate(fuspec):
 154                     src = fu.src_i[idx]
 155
 156                     # connect request-read to picker input, and output to go-rd
 157                     fu_active = fu_bitdict[funame]
 158                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 159                     comb += rdpick.i[pi].eq(pick)
 160                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 161
 162                     # connect regfile port to input, creating a Broadcast Bus
 163                     print ("reg connect widths",
 164                            regfile, regname, pi, funame,
 165                            src.shape(), rport.data_o.shape())
 166                     comb += src.eq(rport.data_o) # all FUs connect to same port
 167
 168     def connect_wrports(self, m, fu_bitdict):
 169         """connect write ports
 170
 171         orders the write regspecs into a dict-of-dicts, by regfile,
 172         by regport name, then connects all FUs that want that regport
 173         by way of a PriorityPicker.
 174
 175         note that the write-port wen, write-port data, and go_wr_i all need to
 176         be on the exact same clock cycle.  as there is a combinatorial loop bug
 177         at the moment, these all use sync.
 178         """
 179         comb, sync = m.d.comb, m.d.sync
 180         fus = self.fus.fus
 181         regs = self.regs
 182         # dictionary of lists of regfile write ports
 183         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 184
 185         # same for write ports.
 186         # BLECH!  complex code-duplication! BLECH!
 187         wrpickers = {}
 188         for regfile, spec in byregfiles_wr.items():
 189             fuspecs = byregfiles_wrspec[regfile]
 190             wrpickers[regfile] = {}
 191             for (regname, fspec) in sort_fuspecs(fuspecs):
 192                 print ("connect wr", regname, fspec)
 193                 rpidx = regname
 194                 # get the regfile specs for this regfile port
 195                 (rf, read, write, wid, fuspec) = fspec
 196
 197                 # select the required write port.  these are pre-defined sizes
 198                 print (regfile, regs.rf.keys())
 199                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 200
 201                 # create a priority picker to manage this port
 202                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 203                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 204
 205                 # connect the regspec write "reg select" number to this port
 206                 # only if one FU actually requests (and is granted) the port
 207                 # will the write-enable be activated
 208                 with m.If(wrpick.en_o):
 209                     sync += wport.wen.eq(write)
 210                 with m.Else():
 211                     sync += wport.wen.eq(0)
 212
 213                 # connect up the FU req/go signals and the reg-read to the FU
 214                 # these are arbitrated by Data.ok signals
 215                 wsigs = []
 216                 for pi, (funame, fu, idx) in enumerate(fuspec):
 217                     # write-request comes from dest.ok
 218                     dest = fu.get_out(idx)
 219                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 220                     wrflag = Signal(name=name, reset_less=True)
 221                     comb += wrflag.eq(dest.ok)
 222
 223                     # connect request-read to picker input, and output to go-wr
 224                     fu_active = fu_bitdict[funame]
 225                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 226                     comb += wrpick.i[pi].eq(pick)
 227                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 228                     # connect regfile port to input
 229                     print ("reg connect widths",
 230                            regfile, regname, pi, funame,
 231                            dest.shape(), wport.data_i.shape())
 232                     wsigs.append(dest)
 233
 234                 # here is where we create the Write Broadcast Bus. simple, eh?
 235                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 236
 237     def get_byregfiles(self, readmode):
 238
 239         mode = "read" if readmode else "write"
 240         dec2 = self.pdecode2
 241         regs = self.regs
 242         fus = self.fus.fus
 243
 244         # dictionary of lists of regfile ports
 245         byregfiles = {}
 246         byregfiles_spec = {}
 247         for (funame, fu) in fus.items():
 248             print ("%s ports for %s" % (mode, funame))
 249             for idx in range(fu.n_src if readmode else fu.n_dst):
 250                 if readmode:
 251                     (regfile, regname, wid) = fu.get_in_spec(idx)
 252                 else:
 253                     (regfile, regname, wid) = fu.get_out_spec(idx)
 254                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 255                 if readmode:
 256                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 257                     write = None
 258                 else:
 259                     rdflag, read = None, None
 260                     wrport, write = dec2.regspecmap_write(regfile, regname)
 261                 if regfile not in byregfiles:
 262                     byregfiles[regfile] = {}
 263                     byregfiles_spec[regfile] = {}
 264                 if regname not in byregfiles_spec[regfile]:
 265                     byregfiles_spec[regfile][regname] = \
 266                                 [rdflag, read, write, wid, []]
 267                 # here we start to create "lanes"
 268                 if idx not in byregfiles[regfile]:
 269                     byregfiles[regfile][idx] = []
 270                 fuspec = (funame, fu, idx)
 271                 byregfiles[regfile][idx].append(fuspec)
 272                 byregfiles_spec[regfile][regname][4].append(fuspec)
 273
 274         # ok just print that out, for convenience
 275         for regfile, spec in byregfiles.items():
 276             print ("regfile %s ports:" % mode, regfile)
 277             fuspecs = byregfiles_spec[regfile]
 278             for regname, fspec in fuspecs.items():
 279                 [rdflag, read, write, wid, fuspec] = fspec
 280                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 281                 print ("  %s" % regname, wid, read, write, rdflag)
 282                 for (funame, fu, idx) in fuspec:
 283                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 284                     print ("    ", funame, fu, idx, fusig)
 285                     print ()
 286
 287         return byregfiles, byregfiles_spec
 288
 289     def __iter__(self):
 290         yield from self.fus.ports()
 291         yield from self.pdecode2.ports()
 292         # TODO: regs
 293
 294     def ports(self):
 295         return list(self)
 296
 297
 298 if __name__ == '__main__':
 299     dut = NonProductionCore()
 300     vl = rtlil.convert(dut, ports=dut.ports())
 301     with open("non_production_core.il", "w") as f:
 302         f.write(vl)