3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
23 from nmigen
.cli
import rtlil
25 from nmutil
.picker
import PriorityPicker
26 from nmutil
.util
import treereduce
28 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
29 from soc
.regfile
.regfiles
import RegFiles
30 from soc
.decoder
.power_decoder
import create_pdecode
31 from soc
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.decoder
.decode2execute1
import Data
33 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
34 from soc
.config
.test
.test_loadstore
import TestMemPspec
35 from soc
.decoder
.power_enums
import MicrOp
38 from nmutil
.util
import rising_edge
41 # helper function for reducing a list of signals down to a parallel
43 def ortreereduce(tree
, attr
="data_o"):
44 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
47 def ortreereduce_sig(tree
):
48 return treereduce(tree
, operator
.or_
, lambda x
: x
)
51 # helper function to place full regs declarations first
52 def sort_fuspecs(fuspecs
):
54 for (regname
, fspec
) in fuspecs
.items():
55 if regname
.startswith("full"):
56 res
.append((regname
, fspec
))
57 for (regname
, fspec
) in fuspecs
.items():
58 if not regname
.startswith("full"):
59 res
.append((regname
, fspec
))
60 return res
# enumerate(res)
63 class NonProductionCore(Elaboratable
):
64 def __init__(self
, pspec
):
65 # single LD/ST funnel for memory access
66 self
.l0
= TstL0CacheBuffer(pspec
, n_units
=1)
67 pi
= self
.l0
.l0
.dports
[0]
69 # function units (only one each)
70 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
72 # register files (yes plural)
73 self
.regs
= RegFiles()
76 pdecode
= create_pdecode()
77 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
79 # issue/valid/busy signalling
80 self
.ivalid_i
= self
.pdecode2
.valid
# instruction is valid
81 self
.issue_i
= Signal(reset_less
=True)
82 self
.busy_o
= Signal(name
="corebusy_o", reset_less
=True)
85 self
.bigendian_i
= self
.pdecode2
.dec
.bigendian
86 self
.raw_opcode_i
= self
.pdecode2
.dec
.raw_opcode_in
88 # start/stop and terminated signalling
89 self
.core_stopped_i
= Signal(reset_less
=True)
90 self
.core_reset_i
= Signal()
91 self
.core_terminate_o
= Signal(reset
=0) # indicates stopped
93 def elaborate(self
, platform
):
96 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
97 m
.submodules
.fus
= self
.fus
98 m
.submodules
.l0
= l0
= self
.l0
99 self
.regs
.elaborate_into(m
, platform
)
103 # connect up Function Units, then read/write ports
104 fu_bitdict
= self
.connect_instruction(m
)
105 self
.connect_rdports(m
, fu_bitdict
)
106 self
.connect_wrports(m
, fu_bitdict
)
109 m
.d
.comb
+= ResetSignal().eq(self
.core_reset_i
)
113 def connect_instruction(self
, m
):
114 """connect_instruction
116 uses decoded (from PowerOp) function unit information from CSV files
117 to ascertain which Function Unit should deal with the current
120 some (such as OP_ATTN, OP_NOP) are dealt with here, including
121 ignoring it and halting the processor. OP_NOP is a bit annoying
122 because the issuer expects busy flag still to be raised then lowered.
123 (this requires a fake counter to be set).
125 comb
, sync
= m
.d
.comb
, m
.d
.sync
129 # enable-signals for each FU, get one bit for each FU (by name)
130 fu_enable
= Signal(len(fus
), reset_less
=True)
132 for i
, funame
in enumerate(fus
.keys()):
133 fu_bitdict
[funame
] = fu_enable
[i
]
135 # enable the required Function Unit based on the opcode decode
136 # note: this *only* works correctly for simple core when one and
137 # *only* one FU is allocated per instruction
138 for funame
, fu
in fus
.items():
139 fnunit
= fu
.fnunit
.value
140 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
141 comb
+= enable
.eq((dec2
.e
.do
.fn_unit
& fnunit
).bool())
142 comb
+= fu_bitdict
[funame
].eq(enable
)
144 # sigh - need a NOP counter
146 with m
.If(counter
!= 0):
147 sync
+= counter
.eq(counter
- 1)
148 comb
+= self
.busy_o
.eq(1)
150 with m
.If(self
.ivalid_i
): # run only when valid
151 with m
.Switch(dec2
.e
.do
.insn_type
):
152 # check for ATTN: halt if true
153 with m
.Case(MicrOp
.OP_ATTN
):
154 m
.d
.sync
+= self
.core_terminate_o
.eq(1)
156 with m
.Case(MicrOp
.OP_NOP
):
157 sync
+= counter
.eq(2)
158 comb
+= self
.busy_o
.eq(1)
161 # connect up instructions. only one enabled at a time
162 for funame
, fu
in fus
.items():
163 enable
= fu_bitdict
[funame
]
165 # run this FunctionUnit if enabled
167 # route op, issue, busy, read flags and mask to FU
168 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
169 comb
+= fu
.issue_i
.eq(self
.issue_i
)
170 comb
+= self
.busy_o
.eq(fu
.busy_o
)
171 rdmask
= dec2
.rdflags(fu
)
172 comb
+= fu
.rdmaskn
.eq(~rdmask
)
176 def connect_rdport(self
, m
, fu_bitdict
, rdpickers
, regfile
, regname
, fspec
):
177 comb
, sync
= m
.d
.comb
, m
.d
.sync
183 # select the required read port. these are pre-defined sizes
184 print(rpidx
, regfile
, regs
.rf
.keys())
185 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
188 if not isinstance(fspecs
, list):
195 for i
, fspec
in enumerate(fspecs
):
196 # get the regfile specs for this regfile port
197 (rf
, read
, write
, wid
, fuspec
) = fspec
198 print ("fpsec", i
, fspec
, len(fuspec
))
199 ppoffs
.append(pplen
) # record offset for picker
201 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
202 rdflag
= Signal(name
=name
, reset_less
=True)
203 comb
+= rdflag
.eq(rf
)
204 rdflags
.append(rdflag
)
207 print ("pplen", pplen
)
209 # create a priority picker to manage this port
210 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
211 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
214 for i
, fspec
in enumerate(fspecs
):
215 (rf
, read
, write
, wid
, fuspec
) = fspec
216 # connect up the FU req/go signals, and the reg-read to the FU
217 # and create a Read Broadcast Bus
218 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
222 # connect request-read to picker input, and output to go-rd
223 fu_active
= fu_bitdict
[funame
]
225 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
])
226 print (pick
, len(pick
))
227 print (rdpick
.i
, len(rdpick
.i
), pi
)
228 comb
+= rdpick
.i
[pi
].eq(pick
)
229 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
231 # if picked, select read-port "reg select" number to port
232 read_en
= Signal
.like(reads
[i
])
233 comb
+= read_en
.eq(Mux(rdpick
.o
[pi
] & rdpick
.en_o
, reads
[i
], 0))
236 with m
.If(rdpick
.o
[pi
] & rdpick
.en_o
):
237 # connect regfile port to input, creating a Broadcast Bus
238 print("reg connect widths",
239 regfile
, regname
, pi
, funame
,
240 src
.shape(), rport
.data_o
.shape())
241 # all FUs connect to same port
242 comb
+= src
.eq(rport
.data_o
)
244 # or-reduce the muxed read signals
245 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
247 def connect_rdports(self
, m
, fu_bitdict
):
248 """connect read ports
250 orders the read regspecs into a dict-of-dicts, by regfile, by
251 regport name, then connects all FUs that want that regport by
252 way of a PriorityPicker.
254 comb
, sync
= m
.d
.comb
, m
.d
.sync
258 # dictionary of lists of regfile read ports
259 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
261 # okaay, now we need a PriorityPicker per regfile per regfile port
262 # loootta pickers... peter piper picked a pack of pickled peppers...
264 for regfile
, spec
in byregfiles_rd
.items():
265 fuspecs
= byregfiles_rdspec
[regfile
]
266 rdpickers
[regfile
] = {}
268 # argh. an experiment to merge RA and RB in the INT regfile
269 # (we have too many read/write ports)
271 fuspecs
['rbc'] = [fuspecs
.pop('rb')]
272 fuspecs
['rbc'].append(fuspecs
.pop('rc'))
273 if regfile
== 'FAST':
274 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
275 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
277 # for each named regfile port, connect up all FUs to that port
278 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
279 print("connect rd", regname
, fspec
)
280 self
.connect_rdport(m
, fu_bitdict
, rdpickers
, regfile
,
283 def connect_wrport(self
, m
, fu_bitdict
, wrpickers
, regfile
, regname
, fspec
):
284 comb
, sync
= m
.d
.comb
, m
.d
.sync
288 print("connect wr", regname
, fspec
)
291 # select the required write port. these are pre-defined sizes
292 print(regfile
, regs
.rf
.keys())
293 wport
= regs
.rf
[regfile
.lower()].w_ports
[rpidx
]
296 if not isinstance(fspecs
, list):
302 for i
, fspec
in enumerate(fspecs
):
303 # get the regfile specs for this regfile port
304 (rf
, read
, write
, wid
, fuspec
) = fspec
305 print ("fpsec", i
, fspec
, len(fuspec
))
306 ppoffs
.append(pplen
) # record offset for picker
309 # create a priority picker to manage this port
310 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
311 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
315 for i
, fspec
in enumerate(fspecs
):
316 # connect up the FU req/go signals and the reg-read to the FU
317 # these are arbitrated by Data.ok signals
318 (rf
, read
, write
, wid
, fuspec
) = fspec
319 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
322 # write-request comes from dest.ok
323 dest
= fu
.get_out(idx
)
324 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
325 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
326 wrflag
= Signal(name
=name
, reset_less
=True)
327 comb
+= wrflag
.eq(dest
.ok
& fu
.busy_o
)
329 # connect request-write to picker input, and output to go-wr
330 fu_active
= fu_bitdict
[funame
]
331 pick
= fu
.wr
.rel_o
[idx
] & fu_active
# & wrflag
332 comb
+= wrpick
.i
[pi
].eq(pick
)
333 # create a single-pulse go write from the picker output
335 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
336 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
338 # connect the regspec write "reg select" number to this port
339 # only if one FU actually requests (and is granted) the port
340 # will the write-enable be activated
341 write_en
= Signal
.like(write
)
342 comb
+= write_en
.eq(Mux(wr_pick
& wrpick
.en_o
, write
, 0))
343 wens
.append(write_en
)
345 # connect regfile port to input
346 print("reg connect widths",
347 regfile
, regname
, pi
, funame
,
348 dest
.shape(), wport
.data_i
.shape())
349 wsigs
.append(fu_dest_latch
)
351 # here is where we create the Write Broadcast Bus. simple, eh?
352 comb
+= wport
.data_i
.eq(ortreereduce_sig(wsigs
))
353 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
355 def connect_wrports(self
, m
, fu_bitdict
):
356 """connect write ports
358 orders the write regspecs into a dict-of-dicts, by regfile,
359 by regport name, then connects all FUs that want that regport
360 by way of a PriorityPicker.
362 note that the write-port wen, write-port data, and go_wr_i all need to
363 be on the exact same clock cycle. as there is a combinatorial loop bug
364 at the moment, these all use sync.
366 comb
, sync
= m
.d
.comb
, m
.d
.sync
369 # dictionary of lists of regfile write ports
370 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
372 # same for write ports.
373 # BLECH! complex code-duplication! BLECH!
375 for regfile
, spec
in byregfiles_wr
.items():
376 fuspecs
= byregfiles_wrspec
[regfile
]
377 wrpickers
[regfile
] = {}
379 # argh, more port-merging
381 fuspecs
['o'] = [fuspecs
.pop('o')]
382 fuspecs
['o'].append(fuspecs
.pop('o1'))
383 if regfile
== 'FAST':
384 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
385 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
387 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
388 self
.connect_wrport(m
, fu_bitdict
, wrpickers
,
389 regfile
, regname
, fspec
)
391 def get_byregfiles(self
, readmode
):
393 mode
= "read" if readmode
else "write"
398 # dictionary of lists of regfile ports
401 for (funame
, fu
) in fus
.items():
402 print("%s ports for %s" % (mode
, funame
))
403 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
405 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
407 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
408 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
410 rdflag
, read
= dec2
.regspecmap_read(regfile
, regname
)
413 rdflag
, read
= None, None
414 wrport
, write
= dec2
.regspecmap_write(regfile
, regname
)
415 if regfile
not in byregfiles
:
416 byregfiles
[regfile
] = {}
417 byregfiles_spec
[regfile
] = {}
418 if regname
not in byregfiles_spec
[regfile
]:
419 byregfiles_spec
[regfile
][regname
] = \
420 (rdflag
, read
, write
, wid
, [])
421 # here we start to create "lanes"
422 if idx
not in byregfiles
[regfile
]:
423 byregfiles
[regfile
][idx
] = []
424 fuspec
= (funame
, fu
, idx
)
425 byregfiles
[regfile
][idx
].append(fuspec
)
426 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
428 # ok just print that out, for convenience
429 for regfile
, spec
in byregfiles
.items():
430 print("regfile %s ports:" % mode
, regfile
)
431 fuspecs
= byregfiles_spec
[regfile
]
432 for regname
, fspec
in fuspecs
.items():
433 [rdflag
, read
, write
, wid
, fuspec
] = fspec
434 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
435 print(" %s" % regname
, wid
, read
, write
, rdflag
)
436 for (funame
, fu
, idx
) in fuspec
:
437 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
438 print(" ", funame
, fu
, idx
, fusig
)
441 return byregfiles
, byregfiles_spec
444 yield from self
.fus
.ports()
445 yield from self
.pdecode2
.ports()
446 yield from self
.l0
.ports()
453 if __name__
== '__main__':
454 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
459 dut
= NonProductionCore(pspec
)
460 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
461 with
open("test_core.il", "w") as f
: