src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.decoder.decode2execute1 import Data
  33 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
  34 from soc.config.test.test_loadstore import TestMemPspec
  35 from soc.decoder.power_enums import InternalOp
  36 import operator
  37
  38
  39 # helper function for reducing a list of signals down to a parallel
  40 # ORed single signal.
  41 def ortreereduce(tree, attr="data_o"):
  42     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  43
  44
  45 # helper function to place full regs declarations first
  46 def sort_fuspecs(fuspecs):
  47     res = []
  48     for (regname, fspec) in fuspecs.items():
  49         if regname.startswith("full"):
  50             res.append((regname, fspec))
  51     for (regname, fspec) in fuspecs.items():
  52         if not regname.startswith("full"):
  53             res.append((regname, fspec))
  54     return res # enumerate(res)
  55
  56
  57 class NonProductionCore(Elaboratable):
  58     def __init__(self, pspec):
  59         # single LD/ST funnel for memory access
  60         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
  61         pi = self.l0.l0.dports[0]
  62
  63         # function units (only one each)
  64         self.fus = AllFunctionUnits(pspec, pilist=[pi])
  65
  66         # register files (yes plural)
  67         self.regs = RegFiles()
  68
  69         # instruction decoder
  70         pdecode = create_pdecode()
  71         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  72
  73         # issue/valid/busy signalling
  74         self.ivalid_i = self.pdecode2.valid   # instruction is valid
  75         self.issue_i = Signal(reset_less=True)
  76         self.busy_o = Signal(name="corebusy_o", reset_less=True)
  77
  78         # instruction input
  79         self.bigendian_i = self.pdecode2.dec.bigendian
  80         self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
  81
  82         # start/stop and terminated signalling
  83         self.core_start_i = Signal(reset_less=True)
  84         self.core_stop_i = Signal(reset_less=True)
  85         self.core_terminated_o = Signal(reset=1) # indicates stopped
  86
  87     def elaborate(self, platform):
  88         m = Module()
  89
  90         m.submodules.pdecode2 = dec2 = self.pdecode2
  91         m.submodules.fus = self.fus
  92         m.submodules.l0 = l0 = self.l0
  93         self.regs.elaborate_into(m, platform)
  94         regs = self.regs
  95         fus = self.fus.fus
  96
  97         # core start/stopped state
  98         core_stopped = Signal(reset=1) # begins in stopped state
  99
 100         # start/stop signalling
 101         with m.If(self.core_start_i):
 102             m.d.sync += core_stopped.eq(0)
 103         with m.If(self.core_stop_i):
 104             m.d.sync += core_stopped.eq(1)
 105         m.d.comb += self.core_terminated_o.eq(core_stopped)
 106
 107         # connect up Function Units, then read/write ports
 108         fu_bitdict = self.connect_instruction(m, core_stopped)
 109         self.connect_rdports(m, fu_bitdict)
 110         self.connect_wrports(m, fu_bitdict)
 111
 112         return m
 113
 114     def connect_instruction(self, m, core_stopped):
 115         comb, sync = m.d.comb, m.d.sync
 116         fus = self.fus.fus
 117         dec2 = self.pdecode2
 118
 119         # enable-signals for each FU, get one bit for each FU (by name)
 120         fu_enable = Signal(len(fus), reset_less=True)
 121         fu_bitdict = {}
 122         for i, funame in enumerate(fus.keys()):
 123             fu_bitdict[funame] = fu_enable[i]
 124
 125         # only run when allowed and when instruction is valid
 126         can_run = Signal(reset_less=True)
 127         comb += can_run.eq(self.ivalid_i & ~core_stopped)
 128
 129         # sigh - need a NOP counter
 130         counter = Signal(2)
 131         with m.If(counter != 0):
 132             sync += counter.eq(counter - 1)
 133         comb += self.busy_o.eq(counter != 0)
 134
 135         # check for ATTN: halt if true
 136         with m.If(self.ivalid_i & (dec2.e.do.insn_type == InternalOp.OP_ATTN)):
 137             m.d.sync += core_stopped.eq(1)
 138
 139         with m.Elif(self.ivalid_i & (dec2.e.do.insn_type == InternalOp.OP_NOP)):
 140             sync += counter.eq(2)
 141             comb += self.busy_o.eq(1)
 142
 143         with m.Else():
 144             # connect up instructions.  only one is enabled at any given time
 145             for funame, fu in fus.items():
 146                 fnunit = fu.fnunit.value
 147                 enable = Signal(name="en_%s" % funame, reset_less=True)
 148                 comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool() & can_run)
 149
 150                 # run this FunctionUnit if enabled, except if the instruction
 151                 # is "attn" in which case we HALT.
 152                 with m.If(enable):
 153                     # route operand, issue, busy, read flags and mask to FU
 154                     comb += fu.oper_i.eq_from_execute1(dec2.e)
 155                     comb += fu.issue_i.eq(self.issue_i)
 156                     comb += self.busy_o.eq(fu.busy_o)
 157                     rdmask = dec2.rdflags(fu)
 158                     comb += fu.rdmaskn.eq(~rdmask)
 159                     comb += fu_bitdict[funame].eq(enable)
 160
 161         return fu_bitdict
 162
 163     def connect_rdports(self, m, fu_bitdict):
 164         """connect read ports
 165
 166         orders the read regspecs into a dict-of-dicts, by regfile, by
 167         regport name, then connects all FUs that want that regport by
 168         way of a PriorityPicker.
 169         """
 170         comb, sync = m.d.comb, m.d.sync
 171         fus = self.fus.fus
 172         regs = self.regs
 173
 174         # dictionary of lists of regfile read ports
 175         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 176
 177         # okaay, now we need a PriorityPicker per regfile per regfile port
 178         # loootta pickers... peter piper picked a pack of pickled peppers...
 179         rdpickers = {}
 180         for regfile, spec in byregfiles_rd.items():
 181             fuspecs = byregfiles_rdspec[regfile]
 182             rdpickers[regfile] = {}
 183
 184             # for each named regfile port, connect up all FUs to that port
 185             for (regname, fspec) in sort_fuspecs(fuspecs):
 186                 print ("connect rd", regname, fspec)
 187                 rpidx = regname
 188                 # get the regfile specs for this regfile port
 189                 (rf, read, write, wid, fuspec) = fspec
 190                 name = "rdflag_%s_%s" % (regfile, regname)
 191                 rdflag = Signal(name=name, reset_less=True)
 192                 comb += rdflag.eq(rf)
 193
 194                 # select the required read port.  these are pre-defined sizes
 195                 print (rpidx, regfile, regs.rf.keys())
 196                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 197
 198                 # create a priority picker to manage this port
 199                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 200                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 201
 202                 # connect the regspec "reg select" number to this port
 203                 with m.If(rdpick.en_o):
 204                     comb += rport.ren.eq(read)
 205
 206                 # connect up the FU req/go signals, and the reg-read to the FU
 207                 # and create a Read Broadcast Bus
 208                 for pi, (funame, fu, idx) in enumerate(fuspec):
 209                     src = fu.src_i[idx]
 210
 211                     # connect request-read to picker input, and output to go-rd
 212                     fu_active = fu_bitdict[funame]
 213                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 214                     comb += rdpick.i[pi].eq(pick)
 215                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 216
 217                     # connect regfile port to input, creating a Broadcast Bus
 218                     print ("reg connect widths",
 219                            regfile, regname, pi, funame,
 220                            src.shape(), rport.data_o.shape())
 221                     comb += src.eq(rport.data_o) # all FUs connect to same port
 222
 223     def connect_wrports(self, m, fu_bitdict):
 224         """connect write ports
 225
 226         orders the write regspecs into a dict-of-dicts, by regfile,
 227         by regport name, then connects all FUs that want that regport
 228         by way of a PriorityPicker.
 229
 230         note that the write-port wen, write-port data, and go_wr_i all need to
 231         be on the exact same clock cycle.  as there is a combinatorial loop bug
 232         at the moment, these all use sync.
 233         """
 234         comb, sync = m.d.comb, m.d.sync
 235         fus = self.fus.fus
 236         regs = self.regs
 237         # dictionary of lists of regfile write ports
 238         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 239
 240         # same for write ports.
 241         # BLECH!  complex code-duplication! BLECH!
 242         wrpickers = {}
 243         for regfile, spec in byregfiles_wr.items():
 244             fuspecs = byregfiles_wrspec[regfile]
 245             wrpickers[regfile] = {}
 246             for (regname, fspec) in sort_fuspecs(fuspecs):
 247                 print ("connect wr", regname, fspec)
 248                 rpidx = regname
 249                 # get the regfile specs for this regfile port
 250                 (rf, read, write, wid, fuspec) = fspec
 251
 252                 # select the required write port.  these are pre-defined sizes
 253                 print (regfile, regs.rf.keys())
 254                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 255
 256                 # create a priority picker to manage this port
 257                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 258                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 259
 260                 # connect the regspec write "reg select" number to this port
 261                 # only if one FU actually requests (and is granted) the port
 262                 # will the write-enable be activated
 263                 with m.If(wrpick.en_o):
 264                     sync += wport.wen.eq(write)
 265                 with m.Else():
 266                     sync += wport.wen.eq(0)
 267
 268                 # connect up the FU req/go signals and the reg-read to the FU
 269                 # these are arbitrated by Data.ok signals
 270                 wsigs = []
 271                 for pi, (funame, fu, idx) in enumerate(fuspec):
 272                     # write-request comes from dest.ok
 273                     dest = fu.get_out(idx)
 274                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 275                     wrflag = Signal(name=name, reset_less=True)
 276                     comb += wrflag.eq(dest.ok)
 277
 278                     # connect request-read to picker input, and output to go-wr
 279                     fu_active = fu_bitdict[funame]
 280                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 281                     comb += wrpick.i[pi].eq(pick)
 282                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 283                     # connect regfile port to input
 284                     print ("reg connect widths",
 285                            regfile, regname, pi, funame,
 286                            dest.shape(), wport.data_i.shape())
 287                     wsigs.append(dest)
 288
 289                 # here is where we create the Write Broadcast Bus. simple, eh?
 290                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 291
 292     def get_byregfiles(self, readmode):
 293
 294         mode = "read" if readmode else "write"
 295         dec2 = self.pdecode2
 296         regs = self.regs
 297         fus = self.fus.fus
 298
 299         # dictionary of lists of regfile ports
 300         byregfiles = {}
 301         byregfiles_spec = {}
 302         for (funame, fu) in fus.items():
 303             print ("%s ports for %s" % (mode, funame))
 304             for idx in range(fu.n_src if readmode else fu.n_dst):
 305                 if readmode:
 306                     (regfile, regname, wid) = fu.get_in_spec(idx)
 307                 else:
 308                     (regfile, regname, wid) = fu.get_out_spec(idx)
 309                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 310                 if readmode:
 311                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 312                     write = None
 313                 else:
 314                     rdflag, read = None, None
 315                     wrport, write = dec2.regspecmap_write(regfile, regname)
 316                 if regfile not in byregfiles:
 317                     byregfiles[regfile] = {}
 318                     byregfiles_spec[regfile] = {}
 319                 if regname not in byregfiles_spec[regfile]:
 320                     byregfiles_spec[regfile][regname] = \
 321                                 [rdflag, read, write, wid, []]
 322                 # here we start to create "lanes"
 323                 if idx not in byregfiles[regfile]:
 324                     byregfiles[regfile][idx] = []
 325                 fuspec = (funame, fu, idx)
 326                 byregfiles[regfile][idx].append(fuspec)
 327                 byregfiles_spec[regfile][regname][4].append(fuspec)
 328
 329         # ok just print that out, for convenience
 330         for regfile, spec in byregfiles.items():
 331             print ("regfile %s ports:" % mode, regfile)
 332             fuspecs = byregfiles_spec[regfile]
 333             for regname, fspec in fuspecs.items():
 334                 [rdflag, read, write, wid, fuspec] = fspec
 335                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 336                 print ("  %s" % regname, wid, read, write, rdflag)
 337                 for (funame, fu, idx) in fuspec:
 338                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 339                     print ("    ", funame, fu, idx, fusig)
 340                     print ()
 341
 342         return byregfiles, byregfiles_spec
 343
 344     def __iter__(self):
 345         yield from self.fus.ports()
 346         yield from self.pdecode2.ports()
 347         yield from self.l0.ports()
 348         # TODO: regs
 349
 350     def ports(self):
 351         return list(self)
 352
 353
 354 if __name__ == '__main__':
 355     pspec = TestMemPspec(ldst_ifacetype='testpi',
 356                          imem_ifacetype='',
 357                          addr_wid=48,
 358                          mask_wid=8,
 359                          reg_wid=64)
 360     dut = NonProductionCore(pspec)
 361     vl = rtlil.convert(dut, ports=dut.ports())
 362     with open("test_core.il", "w") as f:
 363         f.write(vl)