3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 from nmigen
import Elaboratable
, Module
, Signal
8 from nmigen
.cli
import rtlil
10 from nmutil
.picker
import PriorityPicker
11 from nmutil
.util
import treereduce
13 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
14 from soc
.regfile
.regfiles
import RegFiles
15 from soc
.decoder
.power_decoder
import create_pdecode
16 from soc
.decoder
.power_decoder2
import PowerDecode2
20 def ortreereduce(tree
, attr
="data_o"):
21 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
24 class NonProductionCore(Elaboratable
):
26 self
.fus
= AllFunctionUnits()
27 self
.regs
= RegFiles()
28 self
.pdecode
= pdecode
= create_pdecode()
29 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
30 self
.ivalid_i
= self
.pdecode2
.e
.valid
# instruction is valid
32 def elaborate(self
, platform
):
36 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
37 m
.submodules
.fus
= self
.fus
38 self
.regs
.elaborate_into(m
, platform
)
42 # connect up instructions
43 for funame
, fu
in fus
.items():
44 fnunit
= fu
.fnunit
.value
45 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
46 comb
+= enable
.eq(self
.ivalid_i
& (dec2
.e
.fn_unit
& fnunit
!= 0))
48 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
50 # enable-signals for each FU, get one bit for each FU (by name)
51 fu_enable
= Signal(len(fus
), reset_less
=True)
53 for i
, funame
in enumerate(fus
.keys()):
54 fu_bitdict
[funame
] = fu_enable
[i
]
56 # dictionary of lists of regfile read ports
58 byregfiles_rdspec
= {}
59 for (funame
, fu
) in fus
.items():
60 print ("read ports for %s" % funame
)
61 for idx
in range(fu
.n_src
):
62 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
63 print (" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
64 rdflag
, read
, _
= dec2
.regspecmap(regfile
, regname
)
65 if regfile
not in byregfiles_rd
:
66 byregfiles_rd
[regfile
] = {}
67 byregfiles_rdspec
[regfile
] = {}
68 if regname
not in byregfiles_rdspec
[regfile
]:
69 byregfiles_rdspec
[regfile
][regname
] = \
70 [rdflag
, read
, wid
, []]
71 # here we start to create "lanes"
72 if idx
not in byregfiles_rd
[regfile
]:
73 byregfiles_rd
[regfile
][idx
] = []
74 fuspec
= (funame
, fu
, idx
)
75 byregfiles_rd
[regfile
][idx
].append(fuspec
)
76 byregfiles_rdspec
[regfile
][regname
][3].append(fuspec
)
78 # ok just print that out, for convenience
79 for regfile
, spec
in byregfiles_rd
.items():
80 print ("regfile read ports:", regfile
)
81 fuspecs
= byregfiles_rdspec
[regfile
]
82 for regname
, fspec
in fuspecs
.items():
83 [rdflag
, read
, wid
, fuspec
] = fspec
84 print (" regfile read port %s lane: %s" % (regfile
, regname
))
85 print (" %s" % regname
, wid
, read
, rdflag
)
86 for (funame
, fu
, idx
) in fuspec
:
87 print (" ", funame
, fu
, idx
, fu
.src_i
[idx
])
90 # okaay, now we need a PriorityPicker per regfile per regfile port
91 # loootta pickers... peter piper picked a pack of pickled peppers...
93 for regfile
, spec
in byregfiles_rd
.items():
94 fuspecs
= byregfiles_rdspec
[regfile
]
95 rdpickers
[regfile
] = {}
96 for rpidx
, (regname
, fspec
) in enumerate(fuspecs
.items()):
97 # get the regfile specs for this regfile port
98 (rf
, read
, wid
, fuspec
) = fspec
99 name
= "rdflag_%s_%s" % (regfile
, regname
)
100 rdflag
= Signal(name
=name
, reset_less
=True)
101 comb
+= rdflag
.eq(rf
)
103 # "munge" the regfile port index, due to full-port access
104 if regfile
in ['XER', 'CA']:
105 if regname
.startswith('full'):
106 rpidx
= 0 # by convention, first port
108 rpidx
+= 1 # start indexing port 0 from 1
110 # select the required read port. these are pre-defined sizes
111 print (regfile
, regs
.rf
.keys())
112 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
114 # create a priority picker to manage this port
115 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(len(fuspec
))
116 setattr(m
.submodules
, "rdpick_%s_%d" % (regfile
, rpidx
), rdpick
)
118 # connect the regspec "reg select" number to this port
119 with m
.If(rdpick
.en_o
):
120 comb
+= rport
.ren
.eq(read
)
122 # connect up the FU req/go signals and the reg-read to the FU
123 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
124 # connect request-read to picker input, and output to go-rd
125 fu_active
= fu_bitdict
[funame
]
126 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
127 comb
+= rdpick
.i
[pi
].eq(pick
)
128 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
129 # connect regfile port to input
130 print ("reg connect widths",
131 regfile
, regname
, pi
, funame
,
132 fu
.src_i
[idx
].shape(), rport
.data_o
.shape())
133 comb
+= fu
.src_i
[idx
].eq(rport
.data_o
)
138 yield from self
.fus
.ports()
139 yield from self
.pdecode2
.ports()
146 if __name__
== '__main__':
147 dut
= NonProductionCore()
148 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
149 with
open("non_production_core.il", "w") as f
: