src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
  33 from soc.experiment.testmem import TestMemory # test only for instructions
  34 import operator
  35
  36
  37 # helper function for reducing a list of signals down to a parallel
  38 # ORed single signal.
  39 def ortreereduce(tree, attr="data_o"):
  40     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  41
  42 # helper function to place full regs declarations first
  43 def sort_fuspecs(fuspecs):
  44     res = []
  45     for (regname, fspec) in fuspecs.items():
  46         if regname.startswith("full"):
  47             res.append((regname, fspec))
  48     for (regname, fspec) in fuspecs.items():
  49         if not regname.startswith("full"):
  50             res.append((regname, fspec))
  51     return res # enumerate(res)
  52
  53
  54 class NonProductionCore(Elaboratable):
  55     def __init__(self, addrwid=6, idepth=16):
  56         # single LD/ST funnel for memory access
  57         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
  58         pi = self.l0.l0.dports[0].pi
  59
  60         # Test Instruction memory
  61         #self.imem = TestMemory(32, idepth)
  62
  63         # function units (only one each)
  64         self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)
  65
  66         # register files (yes plural)
  67         self.regs = RegFiles()
  68
  69         # instruction decoder
  70         self.pdecode = pdecode = create_pdecode()
  71         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  72
  73         # issue/valid/busy signalling
  74         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  75         self.issue_i = Signal(reset_less=True)
  76         self.busy_o = Signal(reset_less=True)
  77
  78         # instruction input
  79         self.bigendian_i = self.pdecode2.dec.bigendian
  80         self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
  81
  82     def elaborate(self, platform):
  83         m = Module()
  84
  85         m.submodules.pdecode2 = dec2 = self.pdecode2
  86         m.submodules.fus = self.fus
  87         m.submodules.l0 = l0 = self.l0
  88         #m.submodules.imem = imem = self.imem
  89         self.regs.elaborate_into(m, platform)
  90         regs = self.regs
  91         fus = self.fus.fus
  92
  93         fu_bitdict = self.connect_instruction(m)
  94         self.connect_rdports(m, fu_bitdict)
  95         self.connect_wrports(m, fu_bitdict)
  96
  97         return m
  98
  99     def connect_instruction(self, m):
 100         comb, sync = m.d.comb, m.d.sync
 101         fus = self.fus.fus
 102         dec2 = self.pdecode2
 103
 104         # enable-signals for each FU, get one bit for each FU (by name)
 105         fu_enable = Signal(len(fus), reset_less=True)
 106         fu_bitdict = {}
 107         for i, funame in enumerate(fus.keys()):
 108             fu_bitdict[funame] = fu_enable[i]
 109
 110         # connect up instructions.  only one is enabled at any given time
 111         for funame, fu in fus.items():
 112             fnunit = fu.fnunit.value
 113             enable = Signal(name="en_%s" % funame, reset_less=True)
 114             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
 115             with m.If(enable):
 116                 comb += fu.oper_i.eq_from_execute1(dec2.e)
 117                 comb += fu.issue_i.eq(self.issue_i)
 118                 comb += self.busy_o.eq(fu.busy_o)
 119                 rdmask = dec2.rdflags(fu)
 120                 comb += fu.rdmaskn.eq(~rdmask)
 121             comb += fu_bitdict[funame].eq(enable)
 122
 123         return fu_bitdict
 124
 125     def connect_rdports(self, m, fu_bitdict):
 126         """connect read ports
 127
 128         orders the read regspecs into a dict-of-dicts, by regfile, by
 129         regport name, then connects all FUs that want that regport by
 130         way of a PriorityPicker.
 131         """
 132         comb, sync = m.d.comb, m.d.sync
 133         fus = self.fus.fus
 134         regs = self.regs
 135
 136         # dictionary of lists of regfile read ports
 137         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 138
 139         # okaay, now we need a PriorityPicker per regfile per regfile port
 140         # loootta pickers... peter piper picked a pack of pickled peppers...
 141         rdpickers = {}
 142         for regfile, spec in byregfiles_rd.items():
 143             fuspecs = byregfiles_rdspec[regfile]
 144             rdpickers[regfile] = {}
 145
 146             # for each named regfile port, connect up all FUs to that port
 147             for (regname, fspec) in sort_fuspecs(fuspecs):
 148                 print ("connect rd", regname, fspec)
 149                 rpidx = regname
 150                 # get the regfile specs for this regfile port
 151                 (rf, read, write, wid, fuspec) = fspec
 152                 name = "rdflag_%s_%s" % (regfile, regname)
 153                 rdflag = Signal(name=name, reset_less=True)
 154                 comb += rdflag.eq(rf)
 155
 156                 # select the required read port.  these are pre-defined sizes
 157                 print (rpidx, regfile, regs.rf.keys())
 158                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 159
 160                 # create a priority picker to manage this port
 161                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 162                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 163
 164                 # connect the regspec "reg select" number to this port
 165                 with m.If(rdpick.en_o):
 166                     comb += rport.ren.eq(read)
 167
 168                 # connect up the FU req/go signals, and the reg-read to the FU
 169                 # and create a Read Broadcast Bus
 170                 for pi, (funame, fu, idx) in enumerate(fuspec):
 171                     src = fu.src_i[idx]
 172
 173                     # connect request-read to picker input, and output to go-rd
 174                     fu_active = fu_bitdict[funame]
 175                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 176                     comb += rdpick.i[pi].eq(pick)
 177                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 178
 179                     # connect regfile port to input, creating a Broadcast Bus
 180                     print ("reg connect widths",
 181                            regfile, regname, pi, funame,
 182                            src.shape(), rport.data_o.shape())
 183                     comb += src.eq(rport.data_o) # all FUs connect to same port
 184
 185     def connect_wrports(self, m, fu_bitdict):
 186         """connect write ports
 187
 188         orders the write regspecs into a dict-of-dicts, by regfile,
 189         by regport name, then connects all FUs that want that regport
 190         by way of a PriorityPicker.
 191
 192         note that the write-port wen, write-port data, and go_wr_i all need to
 193         be on the exact same clock cycle.  as there is a combinatorial loop bug
 194         at the moment, these all use sync.
 195         """
 196         comb, sync = m.d.comb, m.d.sync
 197         fus = self.fus.fus
 198         regs = self.regs
 199         # dictionary of lists of regfile write ports
 200         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 201
 202         # same for write ports.
 203         # BLECH!  complex code-duplication! BLECH!
 204         wrpickers = {}
 205         for regfile, spec in byregfiles_wr.items():
 206             fuspecs = byregfiles_wrspec[regfile]
 207             wrpickers[regfile] = {}
 208             for (regname, fspec) in sort_fuspecs(fuspecs):
 209                 print ("connect wr", regname, fspec)
 210                 rpidx = regname
 211                 # get the regfile specs for this regfile port
 212                 (rf, read, write, wid, fuspec) = fspec
 213
 214                 # select the required write port.  these are pre-defined sizes
 215                 print (regfile, regs.rf.keys())
 216                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 217
 218                 # create a priority picker to manage this port
 219                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 220                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 221
 222                 # connect the regspec write "reg select" number to this port
 223                 # only if one FU actually requests (and is granted) the port
 224                 # will the write-enable be activated
 225                 with m.If(wrpick.en_o):
 226                     sync += wport.wen.eq(write)
 227                 with m.Else():
 228                     sync += wport.wen.eq(0)
 229
 230                 # connect up the FU req/go signals and the reg-read to the FU
 231                 # these are arbitrated by Data.ok signals
 232                 wsigs = []
 233                 for pi, (funame, fu, idx) in enumerate(fuspec):
 234                     # write-request comes from dest.ok
 235                     dest = fu.get_out(idx)
 236                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 237                     wrflag = Signal(name=name, reset_less=True)
 238                     comb += wrflag.eq(dest.ok)
 239
 240                     # connect request-read to picker input, and output to go-wr
 241                     fu_active = fu_bitdict[funame]
 242                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 243                     comb += wrpick.i[pi].eq(pick)
 244                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 245                     # connect regfile port to input
 246                     print ("reg connect widths",
 247                            regfile, regname, pi, funame,
 248                            dest.shape(), wport.data_i.shape())
 249                     wsigs.append(dest)
 250
 251                 # here is where we create the Write Broadcast Bus. simple, eh?
 252                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 253
 254     def get_byregfiles(self, readmode):
 255
 256         mode = "read" if readmode else "write"
 257         dec2 = self.pdecode2
 258         regs = self.regs
 259         fus = self.fus.fus
 260
 261         # dictionary of lists of regfile ports
 262         byregfiles = {}
 263         byregfiles_spec = {}
 264         for (funame, fu) in fus.items():
 265             print ("%s ports for %s" % (mode, funame))
 266             for idx in range(fu.n_src if readmode else fu.n_dst):
 267                 if readmode:
 268                     (regfile, regname, wid) = fu.get_in_spec(idx)
 269                 else:
 270                     (regfile, regname, wid) = fu.get_out_spec(idx)
 271                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 272                 if readmode:
 273                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 274                     write = None
 275                 else:
 276                     rdflag, read = None, None
 277                     wrport, write = dec2.regspecmap_write(regfile, regname)
 278                 if regfile not in byregfiles:
 279                     byregfiles[regfile] = {}
 280                     byregfiles_spec[regfile] = {}
 281                 if regname not in byregfiles_spec[regfile]:
 282                     byregfiles_spec[regfile][regname] = \
 283                                 [rdflag, read, write, wid, []]
 284                 # here we start to create "lanes"
 285                 if idx not in byregfiles[regfile]:
 286                     byregfiles[regfile][idx] = []
 287                 fuspec = (funame, fu, idx)
 288                 byregfiles[regfile][idx].append(fuspec)
 289                 byregfiles_spec[regfile][regname][4].append(fuspec)
 290
 291         # ok just print that out, for convenience
 292         for regfile, spec in byregfiles.items():
 293             print ("regfile %s ports:" % mode, regfile)
 294             fuspecs = byregfiles_spec[regfile]
 295             for regname, fspec in fuspecs.items():
 296                 [rdflag, read, write, wid, fuspec] = fspec
 297                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 298                 print ("  %s" % regname, wid, read, write, rdflag)
 299                 for (funame, fu, idx) in fuspec:
 300                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 301                     print ("    ", funame, fu, idx, fusig)
 302                     print ()
 303
 304         return byregfiles, byregfiles_spec
 305
 306     def __iter__(self):
 307         yield from self.fus.ports()
 308         yield from self.pdecode2.ports()
 309         # TODO: regs
 310
 311     def ports(self):
 312         return list(self)
 313
 314
 315 if __name__ == '__main__':
 316     dut = NonProductionCore()
 317     vl = rtlil.convert(dut, ports=dut.ports())
 318     with open("non_production_core.il", "w") as f:
 319         f.write(vl)