src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 import operator
  33
  34
  35 # helper function for reducing a list of signals down to a parallel
  36 # ORed single signal.
  37 def ortreereduce(tree, attr="data_o"):
  38     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  39
  40 # helper function to place full regs declarations first
  41 def sort_fuspecs(fuspecs):
  42     res = []
  43     for (regname, fspec) in fuspecs.items():
  44         if regname.startswith("full"):
  45             res.append((regname, fspec))
  46     for (regname, fspec) in fuspecs.items():
  47         if not regname.startswith("full"):
  48             res.append((regname, fspec))
  49     return res # enumerate(res)
  50
  51
  52 class NonProductionCore(Elaboratable):
  53     def __init__(self):
  54         self.fus = AllFunctionUnits()
  55         self.regs = RegFiles()
  56         self.pdecode = pdecode = create_pdecode()
  57         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  58         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  59         self.issue_i = Signal(reset_less=True)
  60         self.busy_o = Signal(reset_less=True)
  61
  62     def elaborate(self, platform):
  63         m = Module()
  64
  65         m.submodules.pdecode2 = dec2 = self.pdecode2
  66         m.submodules.fus = self.fus
  67         self.regs.elaborate_into(m, platform)
  68         regs = self.regs
  69         fus = self.fus.fus
  70
  71         fu_bitdict = self.connect_instruction(m)
  72         self.connect_rdports(m, fu_bitdict)
  73         self.connect_wrports(m, fu_bitdict)
  74
  75         return m
  76
  77     def connect_instruction(self, m):
  78         comb, sync = m.d.comb, m.d.sync
  79         fus = self.fus.fus
  80         dec2 = self.pdecode2
  81
  82         # enable-signals for each FU, get one bit for each FU (by name)
  83         fu_enable = Signal(len(fus), reset_less=True)
  84         fu_bitdict = {}
  85         for i, funame in enumerate(fus.keys()):
  86             fu_bitdict[funame] = fu_enable[i]
  87
  88         # connect up instructions.  only one is enabled at any given time
  89         for funame, fu in fus.items():
  90             fnunit = fu.fnunit.value
  91             enable = Signal(name="en_%s" % funame, reset_less=True)
  92             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
  93             with m.If(enable):
  94                 comb += fu.oper_i.eq_from_execute1(dec2.e)
  95                 comb += fu.issue_i.eq(self.issue_i)
  96                 comb += self.busy_o.eq(fu.busy_o)
  97                 rdmask = dec2.rdflags(fu)
  98                 comb += fu.rdmaskn.eq(~rdmask)
  99             comb += fu_bitdict[funame].eq(enable)
 100
 101         return fu_bitdict
 102
 103     def connect_rdports(self, m, fu_bitdict):
 104         """connect read ports
 105
 106         orders the read regspecs into a dict-of-dicts, by regfile, by
 107         regport name, then connects all FUs that want that regport by
 108         way of a PriorityPicker.
 109         """
 110         comb, sync = m.d.comb, m.d.sync
 111         fus = self.fus.fus
 112         regs = self.regs
 113
 114         # dictionary of lists of regfile read ports
 115         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 116
 117         # okaay, now we need a PriorityPicker per regfile per regfile port
 118         # loootta pickers... peter piper picked a pack of pickled peppers...
 119         rdpickers = {}
 120         for regfile, spec in byregfiles_rd.items():
 121             fuspecs = byregfiles_rdspec[regfile]
 122             rdpickers[regfile] = {}
 123
 124             # for each named regfile port, connect up all FUs to that port
 125             for (regname, fspec) in sort_fuspecs(fuspecs):
 126                 print ("connect rd", regname, fspec)
 127                 rpidx = regname
 128                 # get the regfile specs for this regfile port
 129                 (rf, read, write, wid, fuspec) = fspec
 130                 name = "rdflag_%s_%s" % (regfile, regname)
 131                 rdflag = Signal(name=name, reset_less=True)
 132                 comb += rdflag.eq(rf)
 133
 134                 # select the required read port.  these are pre-defined sizes
 135                 print (rpidx, regfile, regs.rf.keys())
 136                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 137
 138                 # create a priority picker to manage this port
 139                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 140                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 141
 142                 # connect the regspec "reg select" number to this port
 143                 with m.If(rdpick.en_o):
 144                     comb += rport.ren.eq(read)
 145
 146                 # connect up the FU req/go signals, and the reg-read to the FU
 147                 # and create a Read Broadcast Bus
 148                 for pi, (funame, fu, idx) in enumerate(fuspec):
 149                     src = fu.src_i[idx]
 150
 151                     # connect request-read to picker input, and output to go-rd
 152                     fu_active = fu_bitdict[funame]
 153                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 154                     comb += rdpick.i[pi].eq(pick)
 155                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 156
 157                     # connect regfile port to input, creating a Broadcast Bus
 158                     print ("reg connect widths",
 159                            regfile, regname, pi, funame,
 160                            src.shape(), rport.data_o.shape())
 161                     comb += src.eq(rport.data_o) # all FUs connect to same port
 162
 163     def connect_wrports(self, m, fu_bitdict):
 164         """connect write ports
 165
 166         orders the write regspecs into a dict-of-dicts, by regfile,
 167         by regport name, then connects all FUs that want that regport
 168         by way of a PriorityPicker.
 169
 170         note that the write-port wen, write-port data, and go_wr_i all need to
 171         be on the exact same clock cycle.  as there is a combinatorial loop bug
 172         at the moment, these all use sync.
 173         """
 174         comb, sync = m.d.comb, m.d.sync
 175         fus = self.fus.fus
 176         regs = self.regs
 177         # dictionary of lists of regfile write ports
 178         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 179
 180         # same for write ports.
 181         # BLECH!  complex code-duplication! BLECH!
 182         wrpickers = {}
 183         for regfile, spec in byregfiles_wr.items():
 184             fuspecs = byregfiles_wrspec[regfile]
 185             wrpickers[regfile] = {}
 186             for (regname, fspec) in sort_fuspecs(fuspecs):
 187                 print ("connect wr", regname, fspec)
 188                 rpidx = regname
 189                 # get the regfile specs for this regfile port
 190                 (rf, read, write, wid, fuspec) = fspec
 191
 192                 # select the required write port.  these are pre-defined sizes
 193                 print (regfile, regs.rf.keys())
 194                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 195
 196                 # create a priority picker to manage this port
 197                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 198                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 199
 200                 # connect the regspec write "reg select" number to this port
 201                 # only if one FU actually requests (and is granted) the port
 202                 # will the write-enable be activated
 203                 with m.If(wrpick.en_o):
 204                     sync += wport.wen.eq(write)
 205                 with m.Else():
 206                     sync += wport.wen.eq(0)
 207
 208                 # connect up the FU req/go signals and the reg-read to the FU
 209                 # these are arbitrated by Data.ok signals
 210                 wsigs = []
 211                 for pi, (funame, fu, idx) in enumerate(fuspec):
 212                     # write-request comes from dest.ok
 213                     dest = fu.get_out(idx)
 214                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 215                     wrflag = Signal(name=name, reset_less=True)
 216                     comb += wrflag.eq(dest.ok)
 217
 218                     # connect request-read to picker input, and output to go-wr
 219                     fu_active = fu_bitdict[funame]
 220                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 221                     comb += wrpick.i[pi].eq(pick)
 222                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 223                     # connect regfile port to input
 224                     print ("reg connect widths",
 225                            regfile, regname, pi, funame,
 226                            dest.shape(), wport.data_i.shape())
 227                     wsigs.append(dest)
 228
 229                 # here is where we create the Write Broadcast Bus. simple, eh?
 230                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 231
 232     def get_byregfiles(self, readmode):
 233
 234         mode = "read" if readmode else "write"
 235         dec2 = self.pdecode2
 236         regs = self.regs
 237         fus = self.fus.fus
 238
 239         # dictionary of lists of regfile ports
 240         byregfiles = {}
 241         byregfiles_spec = {}
 242         for (funame, fu) in fus.items():
 243             print ("%s ports for %s" % (mode, funame))
 244             for idx in range(fu.n_src if readmode else fu.n_dst):
 245                 if readmode:
 246                     (regfile, regname, wid) = fu.get_in_spec(idx)
 247                 else:
 248                     (regfile, regname, wid) = fu.get_out_spec(idx)
 249                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 250                 if readmode:
 251                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 252                     write = None
 253                 else:
 254                     rdflag, read = None, None
 255                     wrport, write = dec2.regspecmap_write(regfile, regname)
 256                 if regfile not in byregfiles:
 257                     byregfiles[regfile] = {}
 258                     byregfiles_spec[regfile] = {}
 259                 if regname not in byregfiles_spec[regfile]:
 260                     byregfiles_spec[regfile][regname] = \
 261                                 [rdflag, read, write, wid, []]
 262                 # here we start to create "lanes"
 263                 if idx not in byregfiles[regfile]:
 264                     byregfiles[regfile][idx] = []
 265                 fuspec = (funame, fu, idx)
 266                 byregfiles[regfile][idx].append(fuspec)
 267                 byregfiles_spec[regfile][regname][4].append(fuspec)
 268
 269         # ok just print that out, for convenience
 270         for regfile, spec in byregfiles.items():
 271             print ("regfile %s ports:" % mode, regfile)
 272             fuspecs = byregfiles_spec[regfile]
 273             for regname, fspec in fuspecs.items():
 274                 [rdflag, read, write, wid, fuspec] = fspec
 275                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 276                 print ("  %s" % regname, wid, read, write, rdflag)
 277                 for (funame, fu, idx) in fuspec:
 278                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 279                     print ("    ", funame, fu, idx, fusig)
 280                     print ()
 281
 282         return byregfiles, byregfiles_spec
 283
 284     def __iter__(self):
 285         yield from self.fus.ports()
 286         yield from self.pdecode2.ports()
 287         # TODO: regs
 288
 289     def ports(self):
 290         return list(self)
 291
 292
 293 if __name__ == '__main__':
 294     dut = NonProductionCore()
 295     vl = rtlil.convert(dut, ports=dut.ports())
 296     with open("non_production_core.il", "w") as f:
 297         f.write(vl)