src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 import operator
  33
  34
  35 # helper function for reducing a list of signals down to a parallel
  36 # ORed single signal.
  37 def ortreereduce(tree, attr="data_o"):
  38     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  39
  40
  41 class NonProductionCore(Elaboratable):
  42     def __init__(self):
  43         self.fus = AllFunctionUnits()
  44         self.regs = RegFiles()
  45         self.pdecode = pdecode = create_pdecode()
  46         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  47         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  48         self.issue_i = Signal(reset_less=True)
  49         self.busy_o = Signal(reset_less=True)
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53
  54         m.submodules.pdecode2 = dec2 = self.pdecode2
  55         m.submodules.fus = self.fus
  56         self.regs.elaborate_into(m, platform)
  57         regs = self.regs
  58         fus = self.fus.fus
  59
  60         fu_bitdict = self.connect_instruction(m)
  61         self.connect_rdports(m, fu_bitdict)
  62         self.connect_wrports(m, fu_bitdict)
  63
  64         return m
  65
  66     def connect_instruction(self, m):
  67         comb, sync = m.d.comb, m.d.sync
  68         fus = self.fus.fus
  69         dec2 = self.pdecode2
  70
  71         # enable-signals for each FU, get one bit for each FU (by name)
  72         fu_enable = Signal(len(fus), reset_less=True)
  73         fu_bitdict = {}
  74         for i, funame in enumerate(fus.keys()):
  75             fu_bitdict[funame] = fu_enable[i]
  76
  77         # connect up instructions.  only one is enabled at any given time
  78         for funame, fu in fus.items():
  79             fnunit = fu.fnunit.value
  80             enable = Signal(name="en_%s" % funame, reset_less=True)
  81             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
  82             with m.If(enable):
  83                 comb += fu.oper_i.eq_from_execute1(dec2.e)
  84                 comb += fu.issue_i.eq(self.issue_i)
  85                 comb += self.busy_o.eq(fu.busy_o)
  86                 rdmask = dec2.rdflags(fu)
  87                 comb += fu.rdmaskn.eq(~rdmask)
  88             comb += fu_bitdict[funame].eq(enable)
  89
  90         return fu_bitdict
  91
  92     def connect_rdports(self, m, fu_bitdict):
  93     """connect read ports
  94
  95     orders the read regspecs into a dict-of-dicts, by regfile, by regport name,
  96     then connects all FUs that want that regport by way of a PriorityPicker.
  97     """
  98         comb, sync = m.d.comb, m.d.sync
  99         fus = self.fus.fus
 100         regs = self.regs
 101
 102         # dictionary of lists of regfile read ports
 103         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 104
 105         # okaay, now we need a PriorityPicker per regfile per regfile port
 106         # loootta pickers... peter piper picked a pack of pickled peppers...
 107         rdpickers = {}
 108         for regfile, spec in byregfiles_rd.items():
 109             fuspecs = byregfiles_rdspec[regfile]
 110             rdpickers[regfile] = {}
 111
 112             # for each named regfile port, connect up all FUs to that port
 113             for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
 114                 # get the regfile specs for this regfile port
 115                 (rf, read, write, wid, fuspec) = fspec
 116                 name = "rdflag_%s_%s" % (regfile, regname)
 117                 rdflag = Signal(name=name, reset_less=True)
 118                 comb += rdflag.eq(rf)
 119
 120                 # "munge" the regfile port index, due to full-port access
 121                 if regfile in ['XER', 'CA']:
 122                     if regname.startswith('full'):
 123                         rpidx = 0 # by convention, first port
 124                     else:
 125                         rpidx += 1 # start indexing port 0 from 1
 126
 127                 # select the required read port.  these are pre-defined sizes
 128                 print (regfile, regs.rf.keys())
 129                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 130
 131                 # create a priority picker to manage this port
 132                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 133                 setattr(m.submodules, "rdpick_%s_%d" % (regfile, rpidx), rdpick)
 134
 135                 # connect the regspec "reg select" number to this port
 136                 with m.If(rdpick.en_o):
 137                     comb += rport.ren.eq(read)
 138
 139                 # connect up the FU req/go signals, and the reg-read to the FU
 140                 # and create a Read Broadcast Bus
 141                 for pi, (funame, fu, idx) in enumerate(fuspec):
 142                     src = fu.src_i[idx]
 143
 144                     # connect request-read to picker input, and output to go-rd
 145                     fu_active = fu_bitdict[funame]
 146                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 147                     comb += rdpick.i[pi].eq(pick)
 148                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 149
 150                     # connect regfile port to input, creating a Broadcast Bus
 151                     print ("reg connect widths",
 152                            regfile, regname, pi, funame,
 153                            src.shape(), rport.data_o.shape())
 154                     comb += src.eq(rport.data_o) # all FUs connect to same port
 155
 156     def connect_wrports(self, m, fu_bitdict):
 157     """connect write ports
 158
 159     orders the write regspecs into a dict-of-dicts, by regfile, by regport name,
 160     then connects all FUs that want that regport by way of a PriorityPicker.
 161
 162     note that the write-port wen, write-port data, and go_wr_i all need to
 163     be on the exact same clock cycle.  as there is a combinatorial loop bug
 164     at the moment, these all use sync.
 165     """
 166         comb, sync = m.d.comb, m.d.sync
 167         fus = self.fus.fus
 168         regs = self.regs
 169         # dictionary of lists of regfile write ports
 170         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 171
 172         # same for write ports.
 173         # BLECH!  complex code-duplication! BLECH!
 174         wrpickers = {}
 175         for regfile, spec in byregfiles_wr.items():
 176             fuspecs = byregfiles_wrspec[regfile]
 177             wrpickers[regfile] = {}
 178             for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
 179                 # get the regfile specs for this regfile port
 180                 (rf, read, write, wid, fuspec) = fspec
 181
 182                 # "munge" the regfile port index, due to full-port access
 183                 if regfile in ['XER', 'CA']:
 184                     if regname.startswith('full'):
 185                         rpidx = 0 # by convention, first port
 186                     else:
 187                         rpidx += 1 # start indexing port 0 from 1
 188
 189                 # select the required write port.  these are pre-defined sizes
 190                 print (regfile, regs.rf.keys())
 191                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 192
 193                 # create a priority picker to manage this port
 194                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 195                 setattr(m.submodules, "wrpick_%s_%d" % (regfile, rpidx), wrpick)
 196
 197                 # connect the regspec write "reg select" number to this port
 198                 # only if one FU actually requests (and is granted) the port
 199                 # will the write-enable be activated
 200                 with m.If(wrpick.en_o):
 201                     sync += wport.wen.eq(write)
 202                 with m.Else():
 203                     sync += wport.wen.eq(0)
 204
 205                 # connect up the FU req/go signals and the reg-read to the FU
 206                 # these are arbitrated by Data.ok signals
 207                 wsigs = []
 208                 for pi, (funame, fu, idx) in enumerate(fuspec):
 209                     # write-request comes from dest.ok
 210                     dest = fu.get_out(idx)
 211                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 212                     wrflag = Signal(name=name, reset_less=True)
 213                     comb += wrflag.eq(dest.ok)
 214
 215                     # connect request-read to picker input, and output to go-wr
 216                     fu_active = fu_bitdict[funame]
 217                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 218                     comb += wrpick.i[pi].eq(pick)
 219                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 220                     # connect regfile port to input
 221                     print ("reg connect widths",
 222                            regfile, regname, pi, funame,
 223                            dest.shape(), wport.data_i.shape())
 224                     wsigs.append(dest)
 225
 226                 # here is where we create the Write Broadcast Bus. simple, eh?
 227                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 228
 229     def get_byregfiles(self, readmode):
 230
 231         mode = "read" if readmode else "write"
 232         dec2 = self.pdecode2
 233         regs = self.regs
 234         fus = self.fus.fus
 235
 236         # dictionary of lists of regfile ports
 237         byregfiles = {}
 238         byregfiles_spec = {}
 239         for (funame, fu) in fus.items():
 240             print ("%s ports for %s" % (mode, funame))
 241             for idx in range(fu.n_src if readmode else fu.n_dst):
 242                 if readmode:
 243                     (regfile, regname, wid) = fu.get_in_spec(idx)
 244                 else:
 245                     (regfile, regname, wid) = fu.get_out_spec(idx)
 246                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 247                 rdflag, read, write = dec2.regspecmap(regfile, regname)
 248                 if regfile not in byregfiles:
 249                     byregfiles[regfile] = {}
 250                     byregfiles_spec[regfile] = {}
 251                 if regname not in byregfiles_spec[regfile]:
 252                     byregfiles_spec[regfile][regname] = \
 253                                 [rdflag, read, write, wid, []]
 254                 # here we start to create "lanes"
 255                 if idx not in byregfiles[regfile]:
 256                     byregfiles[regfile][idx] = []
 257                 fuspec = (funame, fu, idx)
 258                 byregfiles[regfile][idx].append(fuspec)
 259                 byregfiles_spec[regfile][regname][4].append(fuspec)
 260
 261         # ok just print that out, for convenience
 262         for regfile, spec in byregfiles.items():
 263             print ("regfile %s ports:" % mode, regfile)
 264             fuspecs = byregfiles_spec[regfile]
 265             for regname, fspec in fuspecs.items():
 266                 [rdflag, read, write, wid, fuspec] = fspec
 267                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 268                 print ("  %s" % regname, wid, read, write, rdflag)
 269                 for (funame, fu, idx) in fuspec:
 270                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 271                     print ("    ", funame, fu, idx, fusig)
 272                     print ()
 273
 274         return byregfiles, byregfiles_spec
 275
 276     def __iter__(self):
 277         yield from self.fus.ports()
 278         yield from self.pdecode2.ports()
 279         # TODO: regs
 280
 281     def ports(self):
 282         return list(self)
 283
 284
 285 if __name__ == '__main__':
 286     dut = NonProductionCore()
 287     vl = rtlil.convert(dut, ports=dut.ports())
 288     with open("non_production_core.il", "w") as f:
 289         f.write(vl)