src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 import operator
  33
  34
  35 # helper function for reducing a list of signals down to a parallel
  36 # ORed single signal.
  37 def ortreereduce(tree, attr="data_o"):
  38     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  39
  40
  41 class NonProductionCore(Elaboratable):
  42     def __init__(self):
  43         self.fus = AllFunctionUnits()
  44         self.regs = RegFiles()
  45         self.pdecode = pdecode = create_pdecode()
  46         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  47         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  48         self.issue_i = Signal(reset_less=True)
  49         self.busy_o = Signal(reset_less=True)
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53
  54         m.submodules.pdecode2 = dec2 = self.pdecode2
  55         m.submodules.fus = self.fus
  56         self.regs.elaborate_into(m, platform)
  57         regs = self.regs
  58         fus = self.fus.fus
  59
  60         fu_bitdict = self.connect_instruction(m)
  61         self.connect_rdports(m, fu_bitdict)
  62         self.connect_wrports(m, fu_bitdict)
  63
  64         return m
  65
  66     def connect_instruction(self, m):
  67         comb, sync = m.d.comb, m.d.sync
  68         fus = self.fus.fus
  69         dec2 = self.pdecode2
  70
  71         # enable-signals for each FU, get one bit for each FU (by name)
  72         fu_enable = Signal(len(fus), reset_less=True)
  73         fu_bitdict = {}
  74         for i, funame in enumerate(fus.keys()):
  75             fu_bitdict[funame] = fu_enable[i]
  76
  77         # connect up instructions.  only one is enabled at any given time
  78         for funame, fu in fus.items():
  79             fnunit = fu.fnunit.value
  80             enable = Signal(name="en_%s" % funame, reset_less=True)
  81             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
  82             with m.If(enable):
  83                 comb += fu.oper_i.eq_from_execute1(dec2.e)
  84                 comb += fu.issue_i.eq(self.issue_i)
  85                 comb += self.busy_o.eq(fu.busy_o)
  86                 rdmask = dec2.rdflags(fu)
  87                 comb += fu.rdmaskn.eq(~rdmask)
  88             comb += fu_bitdict[funame].eq(enable)
  89
  90         return fu_bitdict
  91
  92     def connect_rdports(self, m, fu_bitdict):
  93         comb, sync = m.d.comb, m.d.sync
  94         fus = self.fus.fus
  95         regs = self.regs
  96
  97         # dictionary of lists of regfile read ports
  98         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
  99
 100         # okaay, now we need a PriorityPicker per regfile per regfile port
 101         # loootta pickers... peter piper picked a pack of pickled peppers...
 102         rdpickers = {}
 103         for regfile, spec in byregfiles_rd.items():
 104             fuspecs = byregfiles_rdspec[regfile]
 105             rdpickers[regfile] = {}
 106
 107             # for each named regfile port, connect up all FUs to that port
 108             for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
 109                 # get the regfile specs for this regfile port
 110                 (rf, read, write, wid, fuspec) = fspec
 111                 name = "rdflag_%s_%s" % (regfile, regname)
 112                 rdflag = Signal(name=name, reset_less=True)
 113                 comb += rdflag.eq(rf)
 114
 115                 # "munge" the regfile port index, due to full-port access
 116                 if regfile in ['XER', 'CA']:
 117                     if regname.startswith('full'):
 118                         rpidx = 0 # by convention, first port
 119                     else:
 120                         rpidx += 1 # start indexing port 0 from 1
 121
 122                 # select the required read port.  these are pre-defined sizes
 123                 print (regfile, regs.rf.keys())
 124                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 125
 126                 # create a priority picker to manage this port
 127                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 128                 setattr(m.submodules, "rdpick_%s_%d" % (regfile, rpidx), rdpick)
 129
 130                 # connect the regspec "reg select" number to this port
 131                 with m.If(rdpick.en_o):
 132                     comb += rport.ren.eq(read)
 133
 134                 # connect up the FU req/go signals, and the reg-read to the FU
 135                 # and create a Read Broadcast Bus
 136                 for pi, (funame, fu, idx) in enumerate(fuspec):
 137                     src = fu.src_i[idx]
 138
 139                     # connect request-read to picker input, and output to go-rd
 140                     fu_active = fu_bitdict[funame]
 141                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 142                     comb += rdpick.i[pi].eq(pick)
 143                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 144
 145                     # connect regfile port to input, creating a Broadcast Bus
 146                     print ("reg connect widths",
 147                            regfile, regname, pi, funame,
 148                            src.shape(), rport.data_o.shape())
 149                     comb += src.eq(rport.data_o) # all FUs connect to same port
 150
 151     def connect_wrports(self, m, fu_bitdict):
 152         comb, sync = m.d.comb, m.d.sync
 153         fus = self.fus.fus
 154         regs = self.regs
 155         # dictionary of lists of regfile write ports
 156         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 157
 158         # same for write ports.
 159         # BLECH!  complex code-duplication! BLECH!
 160         wrpickers = {}
 161         for regfile, spec in byregfiles_wr.items():
 162             fuspecs = byregfiles_wrspec[regfile]
 163             wrpickers[regfile] = {}
 164             for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
 165                 # get the regfile specs for this regfile port
 166                 (rf, read, write, wid, fuspec) = fspec
 167
 168                 # "munge" the regfile port index, due to full-port access
 169                 if regfile in ['XER', 'CA']:
 170                     if regname.startswith('full'):
 171                         rpidx = 0 # by convention, first port
 172                     else:
 173                         rpidx += 1 # start indexing port 0 from 1
 174
 175                 # select the required write port.  these are pre-defined sizes
 176                 print (regfile, regs.rf.keys())
 177                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 178
 179                 # create a priority picker to manage this port
 180                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 181                 setattr(m.submodules, "wrpick_%s_%d" % (regfile, rpidx), wrpick)
 182
 183                 # connect the regspec write "reg select" number to this port
 184                 # only if one FU actually requests (and is granted) the port
 185                 # will the write-enable be activated
 186                 with m.If(wrpick.en_o):
 187                     sync += wport.wen.eq(write)
 188                 with m.Else():
 189                     sync += wport.wen.eq(0)
 190
 191                 # connect up the FU req/go signals and the reg-read to the FU
 192                 # these are arbitrated by Data.ok signals
 193                 wsigs = []
 194                 for pi, (funame, fu, idx) in enumerate(fuspec):
 195                     # write-request comes from dest.ok
 196                     dest = fu.get_out(idx)
 197                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 198                     wrflag = Signal(name=name, reset_less=True)
 199                     comb += wrflag.eq(dest.ok)
 200
 201                     # connect request-read to picker input, and output to go-wr
 202                     fu_active = fu_bitdict[funame]
 203                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 204                     comb += wrpick.i[pi].eq(pick)
 205                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 206                     # connect regfile port to input
 207                     print ("reg connect widths",
 208                            regfile, regname, pi, funame,
 209                            dest.shape(), wport.data_i.shape())
 210                     wsigs.append(dest)
 211
 212                 # here is where we create the Write Broadcast Bus. simple, eh?
 213                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 214
 215     def get_byregfiles(self, readmode):
 216
 217         mode = "read" if readmode else "write"
 218         dec2 = self.pdecode2
 219         regs = self.regs
 220         fus = self.fus.fus
 221
 222         # dictionary of lists of regfile ports
 223         byregfiles = {}
 224         byregfiles_spec = {}
 225         for (funame, fu) in fus.items():
 226             print ("%s ports for %s" % (mode, funame))
 227             for idx in range(fu.n_src if readmode else fu.n_dst):
 228                 if readmode:
 229                     (regfile, regname, wid) = fu.get_in_spec(idx)
 230                 else:
 231                     (regfile, regname, wid) = fu.get_out_spec(idx)
 232                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 233                 rdflag, read, write = dec2.regspecmap(regfile, regname)
 234                 if regfile not in byregfiles:
 235                     byregfiles[regfile] = {}
 236                     byregfiles_spec[regfile] = {}
 237                 if regname not in byregfiles_spec[regfile]:
 238                     byregfiles_spec[regfile][regname] = \
 239                                 [rdflag, read, write, wid, []]
 240                 # here we start to create "lanes"
 241                 if idx not in byregfiles[regfile]:
 242                     byregfiles[regfile][idx] = []
 243                 fuspec = (funame, fu, idx)
 244                 byregfiles[regfile][idx].append(fuspec)
 245                 byregfiles_spec[regfile][regname][4].append(fuspec)
 246
 247         # ok just print that out, for convenience
 248         for regfile, spec in byregfiles.items():
 249             print ("regfile %s ports:" % mode, regfile)
 250             fuspecs = byregfiles_spec[regfile]
 251             for regname, fspec in fuspecs.items():
 252                 [rdflag, read, write, wid, fuspec] = fspec
 253                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 254                 print ("  %s" % regname, wid, read, write, rdflag)
 255                 for (funame, fu, idx) in fuspec:
 256                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 257                     print ("    ", funame, fu, idx, fusig)
 258                     print ()
 259
 260         return byregfiles, byregfiles_spec
 261
 262     def __iter__(self):
 263         yield from self.fus.ports()
 264         yield from self.pdecode2.ports()
 265         # TODO: regs
 266
 267     def ports(self):
 268         return list(self)
 269
 270
 271 if __name__ == '__main__':
 272     dut = NonProductionCore()
 273     vl = rtlil.convert(dut, ports=dut.ports())
 274     with open("non_production_core.il", "w") as f:
 275         f.write(vl)