3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
23 from nmigen
.cli
import rtlil
25 from nmutil
.picker
import PriorityPicker
26 from nmutil
.util
import treereduce
28 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
29 from soc
.regfile
.regfiles
import RegFiles
30 from soc
.decoder
.power_decoder
import create_pdecode
31 from soc
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.decoder
.decode2execute1
import Data
33 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
34 from soc
.config
.test
.test_loadstore
import TestMemPspec
38 # helper function for reducing a list of signals down to a parallel
40 def ortreereduce(tree
, attr
="data_o"):
41 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
44 # helper function to place full regs declarations first
45 def sort_fuspecs(fuspecs
):
47 for (regname
, fspec
) in fuspecs
.items():
48 if regname
.startswith("full"):
49 res
.append((regname
, fspec
))
50 for (regname
, fspec
) in fuspecs
.items():
51 if not regname
.startswith("full"):
52 res
.append((regname
, fspec
))
53 return res
# enumerate(res)
56 class NonProductionCore(Elaboratable
):
57 def __init__(self
, pspec
):
58 addrwid
= pspec
.addr_wid
59 # single LD/ST funnel for memory access
60 self
.l0
= TstL0CacheBuffer(pspec
, n_units
=1)
61 pi
= self
.l0
.l0
.dports
[0]
63 # function units (only one each)
64 self
.fus
= AllFunctionUnits(pilist
=[pi
], addrwid
=addrwid
)
66 # register files (yes plural)
67 self
.regs
= RegFiles()
70 pdecode
= create_pdecode()
71 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
73 # issue/valid/busy signalling
74 self
.ivalid_i
= self
.pdecode2
.e
.valid
# instruction is valid
75 self
.issue_i
= Signal(reset_less
=True)
76 self
.busy_o
= Signal(name
="corebusy_o", reset_less
=True)
79 self
.bigendian_i
= self
.pdecode2
.dec
.bigendian
80 self
.raw_opcode_i
= self
.pdecode2
.dec
.raw_opcode_in
82 def elaborate(self
, platform
):
85 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
86 m
.submodules
.fus
= self
.fus
87 m
.submodules
.l0
= l0
= self
.l0
88 self
.regs
.elaborate_into(m
, platform
)
92 fu_bitdict
= self
.connect_instruction(m
)
93 self
.connect_rdports(m
, fu_bitdict
)
94 self
.connect_wrports(m
, fu_bitdict
)
98 def connect_instruction(self
, m
):
99 comb
, sync
= m
.d
.comb
, m
.d
.sync
103 # enable-signals for each FU, get one bit for each FU (by name)
104 fu_enable
= Signal(len(fus
), reset_less
=True)
106 for i
, funame
in enumerate(fus
.keys()):
107 fu_bitdict
[funame
] = fu_enable
[i
]
109 # connect up instructions. only one is enabled at any given time
110 for funame
, fu
in fus
.items():
111 fnunit
= fu
.fnunit
.value
112 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
113 comb
+= enable
.eq(self
.ivalid_i
& (dec2
.e
.fn_unit
& fnunit
).bool())
115 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
116 comb
+= fu
.issue_i
.eq(self
.issue_i
)
117 comb
+= self
.busy_o
.eq(fu
.busy_o
)
118 rdmask
= dec2
.rdflags(fu
)
119 comb
+= fu
.rdmaskn
.eq(~rdmask
)
120 comb
+= fu_bitdict
[funame
].eq(enable
)
124 def connect_rdports(self
, m
, fu_bitdict
):
125 """connect read ports
127 orders the read regspecs into a dict-of-dicts, by regfile, by
128 regport name, then connects all FUs that want that regport by
129 way of a PriorityPicker.
131 comb
, sync
= m
.d
.comb
, m
.d
.sync
135 # dictionary of lists of regfile read ports
136 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
138 # okaay, now we need a PriorityPicker per regfile per regfile port
139 # loootta pickers... peter piper picked a pack of pickled peppers...
141 for regfile
, spec
in byregfiles_rd
.items():
142 fuspecs
= byregfiles_rdspec
[regfile
]
143 rdpickers
[regfile
] = {}
145 # for each named regfile port, connect up all FUs to that port
146 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
147 print ("connect rd", regname
, fspec
)
149 # get the regfile specs for this regfile port
150 (rf
, read
, write
, wid
, fuspec
) = fspec
151 name
= "rdflag_%s_%s" % (regfile
, regname
)
152 rdflag
= Signal(name
=name
, reset_less
=True)
153 comb
+= rdflag
.eq(rf
)
155 # select the required read port. these are pre-defined sizes
156 print (rpidx
, regfile
, regs
.rf
.keys())
157 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
159 # create a priority picker to manage this port
160 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(len(fuspec
))
161 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
163 # connect the regspec "reg select" number to this port
164 with m
.If(rdpick
.en_o
):
165 comb
+= rport
.ren
.eq(read
)
167 # connect up the FU req/go signals, and the reg-read to the FU
168 # and create a Read Broadcast Bus
169 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
172 # connect request-read to picker input, and output to go-rd
173 fu_active
= fu_bitdict
[funame
]
174 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
175 comb
+= rdpick
.i
[pi
].eq(pick
)
176 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
178 # connect regfile port to input, creating a Broadcast Bus
179 print ("reg connect widths",
180 regfile
, regname
, pi
, funame
,
181 src
.shape(), rport
.data_o
.shape())
182 comb
+= src
.eq(rport
.data_o
) # all FUs connect to same port
184 def connect_wrports(self
, m
, fu_bitdict
):
185 """connect write ports
187 orders the write regspecs into a dict-of-dicts, by regfile,
188 by regport name, then connects all FUs that want that regport
189 by way of a PriorityPicker.
191 note that the write-port wen, write-port data, and go_wr_i all need to
192 be on the exact same clock cycle. as there is a combinatorial loop bug
193 at the moment, these all use sync.
195 comb
, sync
= m
.d
.comb
, m
.d
.sync
198 # dictionary of lists of regfile write ports
199 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
201 # same for write ports.
202 # BLECH! complex code-duplication! BLECH!
204 for regfile
, spec
in byregfiles_wr
.items():
205 fuspecs
= byregfiles_wrspec
[regfile
]
206 wrpickers
[regfile
] = {}
207 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
208 print ("connect wr", regname
, fspec
)
210 # get the regfile specs for this regfile port
211 (rf
, read
, write
, wid
, fuspec
) = fspec
213 # select the required write port. these are pre-defined sizes
214 print (regfile
, regs
.rf
.keys())
215 wport
= regs
.rf
[regfile
.lower()].w_ports
[rpidx
]
217 # create a priority picker to manage this port
218 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(len(fuspec
))
219 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
221 # connect the regspec write "reg select" number to this port
222 # only if one FU actually requests (and is granted) the port
223 # will the write-enable be activated
224 with m
.If(wrpick
.en_o
):
225 sync
+= wport
.wen
.eq(write
)
227 sync
+= wport
.wen
.eq(0)
229 # connect up the FU req/go signals and the reg-read to the FU
230 # these are arbitrated by Data.ok signals
232 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
233 # write-request comes from dest.ok
234 dest
= fu
.get_out(idx
)
235 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
236 wrflag
= Signal(name
=name
, reset_less
=True)
237 comb
+= wrflag
.eq(dest
.ok
)
239 # connect request-read to picker input, and output to go-wr
240 fu_active
= fu_bitdict
[funame
]
241 pick
= fu
.wr
.rel
[idx
] & fu_active
#& wrflag
242 comb
+= wrpick
.i
[pi
].eq(pick
)
243 sync
+= fu
.go_wr_i
[idx
].eq(wrpick
.o
[pi
] & wrpick
.en_o
)
244 # connect regfile port to input
245 print ("reg connect widths",
246 regfile
, regname
, pi
, funame
,
247 dest
.shape(), wport
.data_i
.shape())
250 # here is where we create the Write Broadcast Bus. simple, eh?
251 sync
+= wport
.data_i
.eq(ortreereduce(wsigs
, "data"))
253 def get_byregfiles(self
, readmode
):
255 mode
= "read" if readmode
else "write"
260 # dictionary of lists of regfile ports
263 for (funame
, fu
) in fus
.items():
264 print ("%s ports for %s" % (mode
, funame
))
265 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
267 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
269 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
270 print (" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
272 rdflag
, read
= dec2
.regspecmap_read(regfile
, regname
)
275 rdflag
, read
= None, None
276 wrport
, write
= dec2
.regspecmap_write(regfile
, regname
)
277 if regfile
not in byregfiles
:
278 byregfiles
[regfile
] = {}
279 byregfiles_spec
[regfile
] = {}
280 if regname
not in byregfiles_spec
[regfile
]:
281 byregfiles_spec
[regfile
][regname
] = \
282 [rdflag
, read
, write
, wid
, []]
283 # here we start to create "lanes"
284 if idx
not in byregfiles
[regfile
]:
285 byregfiles
[regfile
][idx
] = []
286 fuspec
= (funame
, fu
, idx
)
287 byregfiles
[regfile
][idx
].append(fuspec
)
288 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
290 # ok just print that out, for convenience
291 for regfile
, spec
in byregfiles
.items():
292 print ("regfile %s ports:" % mode
, regfile
)
293 fuspecs
= byregfiles_spec
[regfile
]
294 for regname
, fspec
in fuspecs
.items():
295 [rdflag
, read
, write
, wid
, fuspec
] = fspec
296 print (" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
297 print (" %s" % regname
, wid
, read
, write
, rdflag
)
298 for (funame
, fu
, idx
) in fuspec
:
299 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
300 print (" ", funame
, fu
, idx
, fusig
)
303 return byregfiles
, byregfiles_spec
306 yield from self
.fus
.ports()
307 yield from self
.pdecode2
.ports()
308 yield from self
.l0
.ports()
315 if __name__
== '__main__':
316 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
321 dut
= NonProductionCore(pspec
)
322 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
323 with
open("test_core.il", "w") as f
: