3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
, ResetSignal
23 from nmigen
.cli
import rtlil
25 from nmutil
.picker
import PriorityPicker
26 from nmutil
.util
import treereduce
28 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
29 from soc
.regfile
.regfiles
import RegFiles
30 from soc
.decoder
.power_decoder
import create_pdecode
31 from soc
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.decoder
.decode2execute1
import Data
33 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
34 from soc
.config
.test
.test_loadstore
import TestMemPspec
35 from soc
.decoder
.power_enums
import MicrOp
38 from nmutil
.util
import rising_edge
41 # helper function for reducing a list of signals down to a parallel
43 def ortreereduce(tree
, attr
="data_o"):
44 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
47 def ortreereduce_sig(tree
):
48 return treereduce(tree
, operator
.or_
, lambda x
: x
)
51 # helper function to place full regs declarations first
52 def sort_fuspecs(fuspecs
):
54 for (regname
, fspec
) in fuspecs
.items():
55 if regname
.startswith("full"):
56 res
.append((regname
, fspec
))
57 for (regname
, fspec
) in fuspecs
.items():
58 if not regname
.startswith("full"):
59 res
.append((regname
, fspec
))
60 return res
# enumerate(res)
63 class NonProductionCore(Elaboratable
):
64 def __init__(self
, pspec
):
65 # single LD/ST funnel for memory access
66 self
.l0
= TstL0CacheBuffer(pspec
, n_units
=1)
67 pi
= self
.l0
.l0
.dports
[0]
69 # function units (only one each)
70 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
72 # register files (yes plural)
73 self
.regs
= RegFiles()
76 pdecode
= create_pdecode()
77 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
79 # issue/valid/busy signalling
80 self
.ivalid_i
= self
.pdecode2
.valid
# instruction is valid
81 self
.issue_i
= Signal(reset_less
=True)
82 self
.busy_o
= Signal(name
="corebusy_o", reset_less
=True)
85 self
.bigendian_i
= self
.pdecode2
.dec
.bigendian
86 self
.raw_opcode_i
= self
.pdecode2
.dec
.raw_opcode_in
88 # start/stop and terminated signalling
89 self
.core_stopped_i
= Signal(reset_less
=True)
90 self
.core_reset_i
= Signal()
91 self
.core_terminate_o
= Signal(reset
=0) # indicates stopped
93 def elaborate(self
, platform
):
96 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
97 m
.submodules
.fus
= self
.fus
98 m
.submodules
.l0
= l0
= self
.l0
99 self
.regs
.elaborate_into(m
, platform
)
103 # connect up Function Units, then read/write ports
104 fu_bitdict
= self
.connect_instruction(m
)
105 self
.connect_rdports(m
, fu_bitdict
)
106 self
.connect_wrports(m
, fu_bitdict
)
109 m
.d
.comb
+= ResetSignal().eq(self
.core_reset_i
)
113 def connect_instruction(self
, m
):
114 """connect_instruction
116 uses decoded (from PowerOp) function unit information from CSV files
117 to ascertain which Function Unit should deal with the current
120 some (such as OP_ATTN, OP_NOP) are dealt with here, including
121 ignoring it and halting the processor. OP_NOP is a bit annoying
122 because the issuer expects busy flag still to be raised then lowered.
123 (this requires a fake counter to be set).
125 comb
, sync
= m
.d
.comb
, m
.d
.sync
129 # enable-signals for each FU, get one bit for each FU (by name)
130 fu_enable
= Signal(len(fus
), reset_less
=True)
132 for i
, funame
in enumerate(fus
.keys()):
133 fu_bitdict
[funame
] = fu_enable
[i
]
135 # enable the required Function Unit based on the opcode decode
136 # note: this *only* works correctly for simple core when one and
137 # *only* one FU is allocated per instruction
138 for funame
, fu
in fus
.items():
139 fnunit
= fu
.fnunit
.value
140 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
141 comb
+= enable
.eq((dec2
.e
.do
.fn_unit
& fnunit
).bool())
142 comb
+= fu_bitdict
[funame
].eq(enable
)
144 # sigh - need a NOP counter
146 with m
.If(counter
!= 0):
147 sync
+= counter
.eq(counter
- 1)
148 comb
+= self
.busy_o
.eq(1)
150 with m
.If(self
.ivalid_i
): # run only when valid
151 with m
.Switch(dec2
.e
.do
.insn_type
):
152 # check for ATTN: halt if true
153 with m
.Case(MicrOp
.OP_ATTN
):
154 m
.d
.sync
+= self
.core_terminate_o
.eq(1)
156 with m
.Case(MicrOp
.OP_NOP
):
157 sync
+= counter
.eq(2)
158 comb
+= self
.busy_o
.eq(1)
161 # connect up instructions. only one enabled at a time
162 for funame
, fu
in fus
.items():
163 enable
= fu_bitdict
[funame
]
165 # run this FunctionUnit if enabled
167 # route op, issue, busy, read flags and mask to FU
168 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
169 comb
+= fu
.issue_i
.eq(self
.issue_i
)
170 comb
+= self
.busy_o
.eq(fu
.busy_o
)
171 rdmask
= dec2
.rdflags(fu
)
172 comb
+= fu
.rdmaskn
.eq(~rdmask
)
176 def connect_rdports(self
, m
, fu_bitdict
):
177 """connect read ports
179 orders the read regspecs into a dict-of-dicts, by regfile, by
180 regport name, then connects all FUs that want that regport by
181 way of a PriorityPicker.
183 comb
, sync
= m
.d
.comb
, m
.d
.sync
187 # dictionary of lists of regfile read ports
188 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
190 # okaay, now we need a PriorityPicker per regfile per regfile port
191 # loootta pickers... peter piper picked a pack of pickled peppers...
193 for regfile
, spec
in byregfiles_rd
.items():
194 fuspecs
= byregfiles_rdspec
[regfile
]
195 rdpickers
[regfile
] = {}
197 # for each named regfile port, connect up all FUs to that port
198 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
199 print("connect rd", regname
, fspec
)
201 # get the regfile specs for this regfile port
202 (rf
, read
, write
, wid
, fuspec
) = fspec
203 name
= "rdflag_%s_%s" % (regfile
, regname
)
204 rdflag
= Signal(name
=name
, reset_less
=True)
205 comb
+= rdflag
.eq(rf
)
207 # select the required read port. these are pre-defined sizes
208 print(rpidx
, regfile
, regs
.rf
.keys())
209 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
211 # create a priority picker to manage this port
212 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(
214 setattr(m
.submodules
, "rdpick_%s_%s" %
215 (regfile
, rpidx
), rdpick
)
217 # connect the regspec "reg select" number to this port
218 with m
.If(rdpick
.en_o
):
219 comb
+= rport
.ren
.eq(read
)
221 # connect up the FU req/go signals, and the reg-read to the FU
222 # and create a Read Broadcast Bus
223 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
226 # connect request-read to picker input, and output to go-rd
227 fu_active
= fu_bitdict
[funame
]
228 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
229 comb
+= rdpick
.i
[pi
].eq(pick
)
230 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
232 # connect regfile port to input, creating a Broadcast Bus
233 print("reg connect widths",
234 regfile
, regname
, pi
, funame
,
235 src
.shape(), rport
.data_o
.shape())
236 # all FUs connect to same port
237 comb
+= src
.eq(rport
.data_o
)
239 def connect_wrports(self
, m
, fu_bitdict
):
240 """connect write ports
242 orders the write regspecs into a dict-of-dicts, by regfile,
243 by regport name, then connects all FUs that want that regport
244 by way of a PriorityPicker.
246 note that the write-port wen, write-port data, and go_wr_i all need to
247 be on the exact same clock cycle. as there is a combinatorial loop bug
248 at the moment, these all use sync.
250 comb
, sync
= m
.d
.comb
, m
.d
.sync
253 # dictionary of lists of regfile write ports
254 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
256 # same for write ports.
257 # BLECH! complex code-duplication! BLECH!
259 for regfile
, spec
in byregfiles_wr
.items():
260 fuspecs
= byregfiles_wrspec
[regfile
]
261 wrpickers
[regfile
] = {}
262 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
263 print("connect wr", regname
, fspec
)
265 # get the regfile specs for this regfile port
266 (rf
, read
, write
, wid
, fuspec
) = fspec
268 # select the required write port. these are pre-defined sizes
269 print(regfile
, regs
.rf
.keys())
270 wport
= regs
.rf
[regfile
.lower()].w_ports
[rpidx
]
272 # create a priority picker to manage this port
273 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(
275 setattr(m
.submodules
, "wrpick_%s_%s" %
276 (regfile
, rpidx
), wrpick
)
278 # connect the regspec write "reg select" number to this port
279 # only if one FU actually requests (and is granted) the port
280 # will the write-enable be activated
281 with m
.If(wrpick
.en_o
):
282 comb
+= wport
.wen
.eq(write
)
284 comb
+= wport
.wen
.eq(0)
286 # connect up the FU req/go signals and the reg-read to the FU
287 # these are arbitrated by Data.ok signals
289 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
290 # write-request comes from dest.ok
291 dest
= fu
.get_out(idx
)
292 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
293 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
294 wrflag
= Signal(name
=name
, reset_less
=True)
295 comb
+= wrflag
.eq(dest
.ok
& fu
.busy_o
)
297 # connect request-write to picker input, and output to go-wr
298 fu_active
= fu_bitdict
[funame
]
299 pick
= fu
.wr
.rel_o
[idx
] & fu_active
# & wrflag
300 comb
+= wrpick
.i
[pi
].eq(pick
)
301 # create a single-pulse go write from the picker output
303 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
304 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
305 # connect regfile port to input
306 print("reg connect widths",
307 regfile
, regname
, pi
, funame
,
308 dest
.shape(), wport
.data_i
.shape())
309 wsigs
.append(fu_dest_latch
)
311 # here is where we create the Write Broadcast Bus. simple, eh?
312 comb
+= wport
.data_i
.eq(ortreereduce_sig(wsigs
))
314 def get_byregfiles(self
, readmode
):
316 mode
= "read" if readmode
else "write"
321 # dictionary of lists of regfile ports
324 for (funame
, fu
) in fus
.items():
325 print("%s ports for %s" % (mode
, funame
))
326 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
328 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
330 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
331 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
333 rdflag
, read
= dec2
.regspecmap_read(regfile
, regname
)
336 rdflag
, read
= None, None
337 wrport
, write
= dec2
.regspecmap_write(regfile
, regname
)
338 if regfile
not in byregfiles
:
339 byregfiles
[regfile
] = {}
340 byregfiles_spec
[regfile
] = {}
341 if regname
not in byregfiles_spec
[regfile
]:
342 byregfiles_spec
[regfile
][regname
] = \
343 [rdflag
, read
, write
, wid
, []]
344 # here we start to create "lanes"
345 if idx
not in byregfiles
[regfile
]:
346 byregfiles
[regfile
][idx
] = []
347 fuspec
= (funame
, fu
, idx
)
348 byregfiles
[regfile
][idx
].append(fuspec
)
349 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
351 # ok just print that out, for convenience
352 for regfile
, spec
in byregfiles
.items():
353 print("regfile %s ports:" % mode
, regfile
)
354 fuspecs
= byregfiles_spec
[regfile
]
355 for regname
, fspec
in fuspecs
.items():
356 [rdflag
, read
, write
, wid
, fuspec
] = fspec
357 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
358 print(" %s" % regname
, wid
, read
, write
, rdflag
)
359 for (funame
, fu
, idx
) in fuspec
:
360 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
361 print(" ", funame
, fu
, idx
, fusig
)
364 return byregfiles
, byregfiles_spec
367 yield from self
.fus
.ports()
368 yield from self
.pdecode2
.ports()
369 yield from self
.l0
.ports()
376 if __name__
== '__main__':
377 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
382 dut
= NonProductionCore(pspec
)
383 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
384 with
open("test_core.il", "w") as f
: