3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 from nmigen
import Elaboratable
, Module
, Signal
8 from nmigen
.cli
import rtlil
10 from nmutil
.picker
import PriorityPicker
11 from nmutil
.util
import treereduce
13 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
14 from soc
.regfile
.regfiles
import RegFiles
15 from soc
.decoder
.power_decoder
import create_pdecode
16 from soc
.decoder
.power_decoder2
import PowerDecode2
20 def ortreereduce(tree
, attr
="data_o"):
21 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
24 class NonProductionCore(Elaboratable
):
26 self
.fus
= AllFunctionUnits()
27 self
.regs
= RegFiles()
28 self
.pdecode
= pdecode
= create_pdecode()
29 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
30 self
.ivalid_i
= self
.pdecode2
.e
.valid
# instruction is valid
32 def elaborate(self
, platform
):
36 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
37 m
.submodules
.fus
= self
.fus
38 self
.regs
.elaborate_into(m
, platform
)
42 # enable-signals for each FU, get one bit for each FU (by name)
43 fu_enable
= Signal(len(fus
), reset_less
=True)
45 for i
, funame
in enumerate(fus
.keys()):
46 fu_bitdict
[funame
] = fu_enable
[i
]
48 # dictionary of lists of regfile read ports
50 byregfiles_rdspec
= {}
51 for (funame
, fu
) in fus
.items():
52 print ("read ports for %s" % funame
)
53 for idx
in range(fu
.n_src
):
54 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
55 print (" %s %s %s" % (regfile
, regname
, str(wid
)))
56 rdflag
, read
, _
= dec2
.regspecmap(regfile
, regname
)
57 if regfile
not in byregfiles_rd
:
58 byregfiles_rd
[regfile
] = {}
59 byregfiles_rdspec
[regfile
] = (regname
, rdflag
, read
, wid
)
60 # here we start to create "lanes"
61 if idx
not in byregfiles_rd
[regfile
]:
62 byregfiles_rd
[regfile
][idx
] = []
64 byregfiles_rd
[regfile
][idx
].append(fuspec
)
66 # ok just print that out, for convenience
67 for regfile
, spec
in byregfiles_rd
.items():
68 print ("regfile read ports:", regfile
)
69 for idx
, fuspec
in spec
.items():
70 print (" regfile read port %s lane: %d" % (regfile
, idx
))
71 (regname
, rdflag
, read
, wid
) = byregfiles_rdspec
[regfile
]
72 print (" %s" % regname
, wid
, read
, rdflag
)
73 for (funame
, fu
) in fuspec
:
74 print (" ", funame
, fu
, fu
.src_i
[idx
])
77 # okaay, now we need a PriorityPicker per regfile per regfile port
78 # loootta pickers... peter piper picked a pack of pickled peppers...
80 for regfile
, spec
in byregfiles_rd
.items():
81 rdpickers
[regfile
] = {}
82 for rpidx
, (idx
, fuspec
) in enumerate(spec
.items()):
83 # get the regfile specs for this regfile port
84 (regname
, rdflag
, read
, wid
) = byregfiles_rdspec
[regfile
]
86 # "munge" the regfile port index, due to full-port access
87 if regfile
in ['xer', 'cr']:
88 if regname
.startswith('full'):
89 rpidx
= 0 # by convention, first port
91 rpidx
+= 1 # start indexing port 0 from 1
93 # select the required read port. these are pre-defined sizes
94 print (regfile
, regs
.rf
.keys())
95 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
97 # create a priority picker to manage this port
98 rdpickers
[regfile
][idx
] = rdpick
= PriorityPicker(len(fuspec
))
99 setattr(m
.submodules
, "rdpick_%s_%d" % (regfile
, idx
), rdpick
)
101 # connect the regspec "reg select" number to this port
102 with m
.If(rdpick
.en_o
):
103 comb
+= rport
.ren
.eq(read
)
105 # connect up the FU req/go signals and the reg-read to the FU
106 for pi
, (funame
, fu
) in enumerate(fuspec
):
107 # connect request-read to picker input, and output to go-rd
108 fu_active
= fu_bitdict
[funame
]
109 comb
+= rdpick
.i
[pi
].eq(fu
.rd_rel_o
[idx
] & fu_active
)
110 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
111 # connect regfile port to input
112 comb
+= fu
.src_i
[idx
].eq(rport
.data_o
)
117 yield from self
.fus
.ports()
118 yield from self
.pdecode2
.ports()
125 if __name__
== '__main__':
126 dut
= NonProductionCore()
127 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
128 with
open("non_production_core.il", "w") as f
: